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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals61
  • AMBA Family (APB / AHB / AXI)61
  • Coherence Fabrics (ACE / CHI)61
  • Memory Interfaces (DDR / LPDDR / HBM)61
  • PCIe & CXL61
  • Embedded Peripherals (I2C / SPI / UART)61
  • High-Speed I/O (USB / Ethernet / MIPI)61
    • USB Link & Packet Model
    • Ethernet MAC / PHY Basics
      • Ethernet MAC / PHY Basics: Mechanism
      • Ethernet MAC / PHY Basics: Inputs & Outputs
      • Ethernet MAC / PHY Basics: Reports & Metrics
      • Ethernet MAC / PHY Basics: Debug Playbook
      • Ethernet MAC / PHY Basics: Worked Example
      • Ethernet MAC / PHY Basics: Pitfalls & Red Flags
      • Ethernet MAC / PHY Basics: Interview Drills
      • Ethernet MAC / PHY Basics: Review Checklist
      • Ethernet MAC / PHY Basics: Theory Deep Dive
      • Ethernet MAC / PHY Basics: Design Space
      • Ethernet MAC / PHY Basics: Expanded Case Study
      • Ethernet MAC / PHY Basics: Step-by-Step Walkthrough
      • Ethernet MAC / PHY Basics: Comparison Matrix
      • Ethernet MAC / PHY Basics: Software / Programmer View
      • Ethernet MAC / PHY Basics: Silicon PPA Impact
    • MIPI CSI / DSI Overview
    • High-Speed I/O Debug
    • High-Speed I/O (USB / Ethernet / MIPI): Tricky Q&A
  • Protocol Verification & Compliance61
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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‹Ethernet MAC / PHY Basics
  1. Topics
  2. Bus Protocols
  3. High-Speed I/O (USB / Ethernet / MIPI)
  4. Ethernet MAC / PHY Basics
  5. Ethernet MAC / PHY Basics: Interview Drills

Interface Protocols · All levels

Ethernet MAC / PHY Basics: Interview Drills

Interview Drills for Ethernet MAC / PHY Basics.

On this page

    Interview drills

    Interview Drills for Ethernet MAC / PHY Basics focuses on packet loss, CRC error count, line-rate efficiency. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

    Diagram
    PROMPT
    You see packet loss, CRC error count, line-rate efficiency on Ethernet MAC / PHY Basics. Walk through root cause and fix.
    
    STRONG ANSWER
    1. Names the layer and transaction identity.
    2. Explains Ethernet splits packet framing, MAC behavior, PCS, PHY training, and board/channel constraints.
    3. Requests packet capture, MAC counter dump, PHY status register log.
    4. Proposes one reduced sequence and one system regression.
    
    WEAK ANSWER
    Jumps to widening the interface, increasing FIFO depth, or blaming firmware without evidence.

    Diagram to draw on the whiteboard

    MAC / PCS / PHY split

    Diagram
    ETHERNET STACK
    
      [ software / TCP-IP ]
            |
      [ MAC ]  framing, CRC, addressing
            |  (MII/GMII/XGMII)
      [ PCS ]  encoding, alignment
            |  (SerDes)
      [ PMA/PMD / PHY ] electrical, channel
    
    CRC errors -> usually PCS/PHY/channel, not MAC software.

    Root-cause tree to narrate

    Diagram
    ROOT-CAUSE TREE — Ethernet MAC / PHY Basics
    
    packet loss, CRC error count, line-rate efficiency looks wrong
            |
       reproducible?
         /        \
       no          yes
       |            |
     flaky env   same first transaction every time?
     / seed         /            \
                  yes             no
                   |               |
            protocol rule     timing/reset/PVT
            or config bug     or load-dependent

    Protocol deep dive

    USB/Ethernet/MIPI failures cross MAC counters, PCS framing, PHY adaptation, and channel SI.

    Concept diagram

    Diagram
    HIGH-SPEED STACK
    
    app -> MAC/framing -> PCS/encoding -> SerDes/PHY -> channel
    
    CRC errors often mean PCS/PHY/channel, not TCP.

    Metric graph

    Diagram
    BER vs EQ SETTING
    
    BER
    1e-3 |*
    1e-6 |  *
    1e-9 |     **** usable window
    1e-12|          *
         +-----------------> EQ tap

    Metrics and artifacts to collect

    • CRC error rate

    • retrain count

    • frame drop

    • lane error

    • BER

    Mini case study

    Ethernet link up at 100G but lossy: equalization margin on one lane narrow after package change. Digital counters were clean; PHY margin was not.

    Debug branches

    • If link up but lossy, PHY margin and retrain.

    • If enumeration OK but throughput low, check packet size and DMA batching.

    • If MIPI frame drops, blanking budget and lane polarity.

    Senior review question

    Ask: what is the first transaction that deviates, and which spec rule does it test?

    Key takeaways

    • Connect every protocol claim to a transaction identity and measurable metric.

    • Store the artifact (waveform, log, counter) next to every signoff decision.

    Common pitfalls

    • Debugging timeouts without finding the first bad transaction.

    • Quoting peak bus width without payload efficiency and retry overhead.

    • Treating VIP compliance as a substitute for system integration replay.

    Interview whiteboard

    Draw layers first, then place the failing transaction on the diagram.

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    PreviousNext: Ethernet MAC / PHY Basics: Review Checklist

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    See also

    • Ethernet MAC / PHY Basics: Mechanism
    • Ethernet MAC / PHY Basics: Inputs & Outputs
    • Ethernet MAC / PHY Basics: Reports & Metrics