Ethernet MAC / PHY Basics: Review Checklist

Review checklist

Review Checklist for Ethernet MAC / PHY Basics focuses on packet loss, CRC error count, line-rate efficiency. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

• Spec revision and implemented feature subset are named.

• Clock/reset and CDC assumptions are reviewed.

• Traffic classes, IDs/tags, ordering, and outstanding limits are documented.

• VIP/compliance coverage maps back to requirements.

• Performance metric and debug artifact are stored with the signoff note.

• Owners signed: network IP owner, PHY owner, software owner.

Sign-off ownership

OWNERSHIP MAP — Ethernet MAC / PHY Basics

evidence type        owner who reads it
-----------------    ---------------------------
waveform/RTL        network IP owner
spec/VIP            PHY owner
firmware/system     software owner

Rule: every metric must have a named owner before a review starts.

Protocol deep dive

USB/Ethernet/MIPI failures cross MAC counters, PCS framing, PHY adaptation, and channel SI.

Concept diagram

HIGH-SPEED STACK

app -> MAC/framing -> PCS/encoding -> SerDes/PHY -> channel

CRC errors often mean PCS/PHY/channel, not TCP.

Metric graph

BER vs EQ SETTING

BER
1e-3 |*
1e-6 |  *
1e-9 |     **** usable window
1e-12|          *
     +-----------------> EQ tap

Metrics and artifacts to collect

• CRC error rate

• retrain count

• frame drop

• lane error

• BER

Mini case study

Ethernet link up at 100G but lossy: equalization margin on one lane narrow after package change. Digital counters were clean; PHY margin was not.

Debug branches

• If link up but lossy, PHY margin and retrain.

• If enumeration OK but throughput low, check packet size and DMA batching.

• If MIPI frame drops, blanking budget and lane polarity.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.

Principal review addendum

Re-read Ethernet MAC / PHY Basics against one concrete product workload, not a synthetic directed test.

Ethernet splits packet framing, MAC behavior, PCS, PHY training, and board/channel constraints.