Ethernet MAC / PHY Basics: Theory Deep Dive

Foundational theory

Ethernet MAC / PHY Basics is a core topic in High-Speed I/O (USB / Ethernet / MIPI). Ethernet splits packet framing, MAC behavior, PCS, PHY training, and board/channel constraints. Senior engineers treat it as a contract problem: each boundary must preserve transaction identity, ordering rules, and forward progress under backpressure.

Core concepts explained

• Ethernet splits packet framing, MAC behavior, PCS, PHY training, and board/channel constraints.

• Primary metric: packet loss, CRC error count, line-rate efficiency

• Primary artifact: packet capture, MAC counter dump, PHY status register log

• Owners: network IP owner, PHY owner, software owner

• Layer model: software intent → transaction → channel/link → physical/timing

• Debug posture: find the first deviation, not the loudest timeout

Why this matters in real chips

In silicon integration, Ethernet MAC / PHY Basics failures appear as hung transactions, corrupted data, bandwidth cliffs, or bring-up stalls. High-speed I/O crosses digital framing, PHY adaptation, and channel physics. Without mechanism-first analysis, teams burn weeks widening buses or blaming firmware.

Mental model

ETHERNET STACK

  [ software / TCP-IP ]
        |
  [ MAC ]  framing, CRC, addressing
        |  (MII/GMII/XGMII)
  [ PCS ]  encoding, alignment
        |  (SerDes)
  [ PMA/PMD / PHY ] electrical, channel

CRC errors -> usually PCS/PHY/channel, not MAC software.

Worked intuition

1. Name the workload or traffic class exercising Ethernet MAC / PHY Basics.

2. Open packet loss, CRC error count, line-rate efficiency and identify the failing cluster (p99 often matters more than average).

3. Tag transaction identity: ID, address, endpoint, lane, or cache line.

4. Map the symptom to protocol layer: transaction, link, or physical.

5. Collect packet capture, MAC counter dump, PHY status register log and align timestamp with VIP or analyzer view.

6. Reduce to smallest legal/illegal sequence that reproduces the bug.

7. Propose one bounded fix and list compliance + product regressions.

Common misconceptions

• Handshake activity implies the transaction is legal.

• Peak interface width equals useful payload bandwidth.

• A VIP pass guarantees integrated-system correctness.

• Software timeouts always mean the PHY or link is broken.

• More buffering fixes ordering or coherence bugs without analysis.

Visual reinforcement

MAC / PCS / PHY split

ETHERNET STACK

  [ software / TCP-IP ]
        |
  [ MAC ]  framing, CRC, addressing
        |  (MII/GMII/XGMII)
  [ PCS ]  encoding, alignment
        |  (SerDes)
  [ PMA/PMD / PHY ] electrical, channel

CRC errors -> usually PCS/PHY/channel, not MAC software.

Layer responsibilities

LAYER RESPONSIBILITY — Ethernet MAC / PHY Basics

layer          owns                         common failure
-----------    --------------------------   -----------------------
software       intent, ordering needs       wrong assumption
transaction    id/addr/len/attributes       ordering / outstanding
link/channel   handshake, credits, retry    backpressure / deadlock
physical       clock/reset/lanes/PHY        timing / training / SI
observability  waveform/log/counter         missing evidence

Protocol deep dive

USB/Ethernet/MIPI failures cross MAC counters, PCS framing, PHY adaptation, and channel SI.

Concept diagram

HIGH-SPEED STACK

app -> MAC/framing -> PCS/encoding -> SerDes/PHY -> channel

CRC errors often mean PCS/PHY/channel, not TCP.

Metric graph

BER vs EQ SETTING

BER
1e-3 |*
1e-6 |  *
1e-9 |     **** usable window
1e-12|          *
     +-----------------> EQ tap

Metrics and artifacts to collect

• CRC error rate

• retrain count

• frame drop

• lane error

• BER

Mini case study

Ethernet link up at 100G but lossy: equalization margin on one lane narrow after package change. Digital counters were clean; PHY margin was not.

Debug branches

• If link up but lossy, PHY margin and retrain.

• If enumeration OK but throughput low, check packet size and DMA batching.

• If MIPI frame drops, blanking budget and lane polarity.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.

Theory reinforcement

High-speed I/O crosses digital framing, PHY adaptation, and channel physics.