Review Checklist for MIPI CSI / DSI Overview focuses on lane error rate, frame drop count, blanking budget. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.
Spec revision and implemented feature subset are named.
Clock/reset and CDC assumptions are reviewed.
Traffic classes, IDs/tags, ordering, and outstanding limits are documented.
VIP/compliance coverage maps back to requirements.
Performance metric and debug artifact are stored with the signoff note.
Owners signed: multimedia owner, PHY owner, driver owner.
OWNERSHIP MAP — MIPI CSI / DSI Overview
evidence type owner who reads it
----------------- ---------------------------
waveform/RTL multimedia owner
spec/VIP PHY owner
firmware/system driver owner
Rule: every metric must have a named owner before a review starts.USB/Ethernet/MIPI failures cross MAC counters, PCS framing, PHY adaptation, and channel SI.
HIGH-SPEED STACK
app -> MAC/framing -> PCS/encoding -> SerDes/PHY -> channel
CRC errors often mean PCS/PHY/channel, not TCP.BER vs EQ SETTING
BER
1e-3 |*
1e-6 | *
1e-9 | **** usable window
1e-12| *
+-----------------> EQ tapCRC error rate
retrain count
frame drop
lane error
BER
Ethernet link up at 100G but lossy: equalization margin on one lane narrow after package change. Digital counters were clean; PHY margin was not.
If link up but lossy, PHY margin and retrain.
If enumeration OK but throughput low, check packet size and DMA batching.
If MIPI frame drops, blanking budget and lane polarity.
Ask: what is the first transaction that deviates, and which spec rule does it test?
Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.
Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.
Re-read MIPI CSI / DSI Overview against one concrete product workload, not a synthetic directed test.
MIPI moves camera/display payloads through lane-based high-speed bursts with strict timing and packet framing.
This content block can't be displayed here.
Block type: unknown
This content block can't be displayed here.
Block type: unknown
This content block can't be displayed here.
Block type: unknown