DenseChip

Interface Protocols · All levels

MIPI CSI / DSI Overview: Comparison Matrix

Comparison Matrix for MIPI CSI / DSI Overview.

Comparison matrix

MAC/PCS/PHY split defines where bugs live and which team owns them.

diagram
+------------------+----------------+----------------+----------------+
| Approach         | Strength       | Weakness       | Best when      |
+------------------+----------------+----------------+----------------+
| Baseline         | known, signed  | may miss peak  | shipping SKU   |
| More buffer      | absorbs latency | area, deadlock | DMA-heavy      |
| Wider bus        | peak BW up     | timing, power  | memory bound   |
| SW contract      | cheap silicon  | driver burden  | fixed platform |
+------------------+----------------+----------------+----------------+

When to choose each approach

  • Pick baseline when schedule and risk dominate

  • Pick buffering only after proving backpressure is the limiter

  • Pick width only after payload efficiency analysis

  • Pick software contract when hardware change is too expensive

Interview traps

  • Comparing peak spec numbers across protocols

  • Ignoring bridge and firmware in the comparison

  • One-size-fits-all answer in interviews

Evidence comparison

diagram
COMPLIANCE / DEBUG MATRIX — MIPI CSI / DSI Overview

+-------------------+------------------------+--------------------------+-------------------------+
| Evidence           | Tells you              | Does not prove           | Next action             |
+-------------------+------------------------+--------------------------+-------------------------+
| Waveform           | signal-level sequence  | full system intent       | map to transaction log  |
| VIP transaction    | spec-level behavior    | RTL micro-cause          | correlate timestamp     |
| Counter / PMU      | aggregate symptom      | single failing packet    | isolate traffic class   |
| Firmware log       | software-visible flow  | electrical/link health   | compare with hardware   |
| Analyzer capture   | external protocol view | internal reset/config    | align with RTL trace    |
+-------------------+------------------------+--------------------------+-------------------------+

Protocol deep dive

USB/Ethernet/MIPI failures cross MAC counters, PCS framing, PHY adaptation, and channel SI.

Concept diagram

diagram
HIGH-SPEED STACK

app -> MAC/framing -> PCS/encoding -> SerDes/PHY -> channel

CRC errors often mean PCS/PHY/channel, not TCP.

Metric graph

diagram
BER vs EQ SETTING

BER
1e-3 |*
1e-6 |  *
1e-9 |     **** usable window
1e-12|          *
     +-----------------> EQ tap

Metrics and artifacts to collect

  • CRC error rate

  • retrain count

  • frame drop

  • lane error

  • BER

Mini case study

Ethernet link up at 100G but lossy: equalization margin on one lane narrow after package change. Digital counters were clean; PHY margin was not.

Debug branches

  • If link up but lossy, PHY margin and retrain.

  • If enumeration OK but throughput low, check packet size and DMA batching.

  • If MIPI frame drops, blanking budget and lane polarity.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

  • Connect every protocol claim to a transaction identity and measurable metric.

  • Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

  • Debugging timeouts without finding the first bad transaction.

  • Quoting peak bus width without payload efficiency and retry overhead.

  • Treating VIP compliance as a substitute for system integration replay.

Principal review addendum

Re-read MIPI CSI / DSI Overview against one concrete product workload, not a synthetic directed test.

MIPI moves camera/display payloads through lane-based high-speed bursts with strict timing and packet framing.

Practice this lesson