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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals61
  • AMBA Family (APB / AHB / AXI)61
  • Coherence Fabrics (ACE / CHI)61
  • Memory Interfaces (DDR / LPDDR / HBM)61
  • PCIe & CXL61
  • Embedded Peripherals (I2C / SPI / UART)61
  • High-Speed I/O (USB / Ethernet / MIPI)61
    • USB Link & Packet Model
      • USB Link & Packet Model: Mechanism
      • USB Link & Packet Model: Inputs & Outputs
      • USB Link & Packet Model: Reports & Metrics
      • USB Link & Packet Model: Debug Playbook
      • USB Link & Packet Model: Worked Example
      • USB Link & Packet Model: Pitfalls & Red Flags
      • USB Link & Packet Model: Interview Drills
      • USB Link & Packet Model: Review Checklist
      • USB Link & Packet Model: Theory Deep Dive
      • USB Link & Packet Model: Design Space
      • USB Link & Packet Model: Expanded Case Study
      • USB Link & Packet Model: Step-by-Step Walkthrough
      • USB Link & Packet Model: Comparison Matrix
      • USB Link & Packet Model: Software / Programmer View
      • USB Link & Packet Model: Silicon PPA Impact
    • Ethernet MAC / PHY Basics
    • MIPI CSI / DSI Overview
    • High-Speed I/O Debug
    • High-Speed I/O (USB / Ethernet / MIPI): Tricky Q&A
  • Protocol Verification & Compliance61
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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‹USB Link & Packet Model
  1. Topics
  2. Bus Protocols
  3. High-Speed I/O (USB / Ethernet / MIPI)
  4. USB Link & Packet Model
  5. USB Link & Packet Model: Reports & Metrics

Interface Protocols · All levels

USB Link & Packet Model: Reports & Metrics

Reports & Metrics for USB Link & Packet Model.

On this page

    Reports and metrics

    Reports & Metrics for USB Link & Packet Model focuses on enumeration success, retry count, endpoint throughput. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

    The job of a report is to turn enumeration success, retry count, endpoint throughput into a decision. A single average number is almost never enough; you need the distribution, the traffic class breakdown, and a clear gap between legal maximum and product target.

    Metric movement

    Diagram
    METRIC GRAPH — enumeration success, retry count, endpoint throughput
    
    throughput / success
      ^
      |                         target
      |                       - - - - - - -
      |                  o after bounded fix
      |              o
      |         o baseline
      |    o failing run
      +--------------------------------------> experiment
        config A     isolated root cause     accepted change
    
    Readout:
      - compare identical payload, clock, reset, traffic seed, and firmware setup
      - separate headline bandwidth from useful payload bandwidth
      - explain why the protocol mechanism moved the metric

    Latency distribution

    Diagram
    LATENCY HISTOGRAM — USB Link & Packet Model
    
    count
      |               ███
      |             ███████
      |          █████████████
      |        █████████████████        <- long tail = the real complaint
      |      ████████████████████████████
      +------------------------------------> latency
       p50      p90    p95       p99  (watch p99, not the average)
    
    Average hides the tail; product pain lives at p95/p99.
    • Track enumeration success, retry count, endpoint throughput by traffic class, payload size, and clock/reset mode.

    • Report p50/p95/p99 latency when user-visible stalls matter.

    • Include legal maximums and product targets; they are not the same thing.

    • Always store the metric next to the artifact that produced it.

    Protocol deep dive

    USB/Ethernet/MIPI failures cross MAC counters, PCS framing, PHY adaptation, and channel SI.

    Concept diagram

    Diagram
    HIGH-SPEED STACK
    
    app -> MAC/framing -> PCS/encoding -> SerDes/PHY -> channel
    
    CRC errors often mean PCS/PHY/channel, not TCP.

    Metric graph

    Diagram
    BER vs EQ SETTING
    
    BER
    1e-3 |*
    1e-6 |  *
    1e-9 |     **** usable window
    1e-12|          *
         +-----------------> EQ tap

    Metrics and artifacts to collect

    • CRC error rate

    • retrain count

    • frame drop

    • lane error

    • BER

    Mini case study

    Ethernet link up at 100G but lossy: equalization margin on one lane narrow after package change. Digital counters were clean; PHY margin was not.

    Debug branches

    • If link up but lossy, PHY margin and retrain.

    • If enumeration OK but throughput low, check packet size and DMA batching.

    • If MIPI frame drops, blanking budget and lane polarity.

    Senior review question

    Ask: what is the first transaction that deviates, and which spec rule does it test?

    Key takeaways

    • Connect every protocol claim to a transaction identity and measurable metric.

    • Store the artifact (waveform, log, counter) next to every signoff decision.

    Common pitfalls

    • Debugging timeouts without finding the first bad transaction.

    • Quoting peak bus width without payload efficiency and retry overhead.

    • Treating VIP compliance as a substitute for system integration replay.

    How to read the numbers

    enumeration success, retry count, endpoint throughput must be split by traffic class, payload size, and reset mode.

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    See also

    • USB Link & Packet Model: Mechanism
    • USB Link & Packet Model: Worked Example
    • USB Link & Packet Model: Pitfalls & Red Flags