Interface Protocols · All levels

USB Link & Packet Model: Interview Drills

Interview Drills for USB Link & Packet Model.

Interview drills

Interview Drills for USB Link & Packet Model focuses on enumeration success, retry count, endpoint throughput. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

diagram

PROMPT
You see enumeration success, retry count, endpoint throughput on USB Link & Packet Model. Walk through root cause and fix.

STRONG ANSWER
1. Names the layer and transaction identity.
2. Explains USB combines host-driven enumeration, endpoints, packets, link states, and PHY behavior into a software-visible device model.
3. Requests USB analyzer trace, endpoint descriptor dump, link-state timeline.
4. Proposes one reduced sequence and one system regression.

WEAK ANSWER
Jumps to widening the interface, increasing FIFO depth, or blaming firmware without evidence.

Diagram to draw on the whiteboard

USB transfer = token/data/handshake

diagram

USB TRANSACTION

host: TOKEN (IN/OUT/SETUP, addr, endpoint)
        |
        v
data: DATA0/DATA1 packet
        |
        v
ack : HANDSHAKE (ACK/NAK/STALL)

NAK = "not ready, retry" (normal). STALL = "error, software must clear".

Root-cause tree to narrate

diagram

ROOT-CAUSE TREE — USB Link & Packet Model

enumeration success, retry count, endpoint throughput looks wrong
        |
   reproducible?
     /        \
   no          yes
   |            |
 flaky env   same first transaction every time?
 / seed         /            \
              yes             no
               |               |
        protocol rule     timing/reset/PVT
        or config bug     or load-dependent

Protocol deep dive

USB/Ethernet/MIPI failures cross MAC counters, PCS framing, PHY adaptation, and channel SI.

Concept diagram

diagram

HIGH-SPEED STACK

app -> MAC/framing -> PCS/encoding -> SerDes/PHY -> channel

CRC errors often mean PCS/PHY/channel, not TCP.

Metric graph

diagram

BER vs EQ SETTING

BER
1e-3 |*
1e-6 |  *
1e-9 |     **** usable window
1e-12|          *
     +-----------------> EQ tap

Metrics and artifacts to collect

CRC error rate
retrain count
frame drop
lane error
BER

Mini case study

Ethernet link up at 100G but lossy: equalization margin on one lane narrow after package change. Digital counters were clean; PHY margin was not.

Debug branches

If link up but lossy, PHY margin and retrain.
If enumeration OK but throughput low, check packet size and DMA batching.
If MIPI frame drops, blanking budget and lane polarity.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.

Interview whiteboard

Draw layers first, then place the failing transaction on the diagram.

Practice this lesson