PROMPT
You see ready deassertion rate, queue occupancy, throughput collapse point on Handshake & Backpressure. Walk through root cause and fix.

STRONG ANSWER
1. Names the layer and transaction identity.
2. Explains valid/ready, request/grant, and credit schemes move pressure upstream before buffers overflow.
3. Requests waveform with stall windows, credit counter trace, FIFO occupancy graph.
4. Proposes one reduced sequence and one system regression.

WEAK ANSWER
Jumps to widening the interface, increasing FIFO depth, or blaming firmware without evidence.

VALID / READY HANDSHAKE (transfer happens when both are high)

clk     _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_
valid   ____|‾‾‾‾‾‾‾‾‾‾‾|________
ready   ________|‾‾‾‾‾‾‾|____________
xfer              ^   ^
                  |   |
       transfer on cycles where valid & ready are both 1

Read rule:
  - valid must NOT wait for ready (no combinational deadlock)
  - data must stay stable while valid is high and ready is low

ROOT-CAUSE TREE — Handshake & Backpressure

ready deassertion rate, queue occupancy, throughput collapse point looks wrong
        |
   reproducible?
     /        \
   no          yes
   |            |
 flaky env   same first transaction every time?
 / seed         /            \
              yes             no
               |               |
        protocol rule     timing/reset/PVT
        or config bug     or load-dependent

FUNDAMENTALS STACK

software intent
     |
transaction (ID, addr, len, attr, order)
     |
link/channel (handshake, credit, retry)
     |
physical (clock, reset, lanes, PHY)

Debug golden rule: never change layers without carrying transaction identity.

STALL BREAKDOWN EXAMPLE

ready stalls      ████████████████  42%
credit wait       ██████████        26%
ordering block    ██████            16%
reset/config      ████              10%
other             ██                6%

If ready stalls dominate, widening the bus will not help.