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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals61
    • Layering & Transaction Model
    • Handshake & Backpressure
      • Handshake & Backpressure: Mechanism
      • Handshake & Backpressure: Inputs & Outputs
      • Handshake & Backpressure: Reports & Metrics
      • Handshake & Backpressure: Debug Playbook
      • Handshake & Backpressure: Worked Example
      • Handshake & Backpressure: Pitfalls & Red Flags
      • Handshake & Backpressure: Interview Drills
      • Handshake & Backpressure: Review Checklist
      • Handshake & Backpressure: Theory Deep Dive
      • Handshake & Backpressure: Design Space
      • Handshake & Backpressure: Expanded Case Study
      • Handshake & Backpressure: Step-by-Step Walkthrough
      • Handshake & Backpressure: Comparison Matrix
      • Handshake & Backpressure: Software / Programmer View
      • Handshake & Backpressure: Silicon PPA Impact
    • Ordering & Outstanding Rules
    • Bandwidth & Latency Budgeting
    • Protocol Fundamentals: Tricky Q&A
  • AMBA Family (APB / AHB / AXI)61
  • Coherence Fabrics (ACE / CHI)61
  • Memory Interfaces (DDR / LPDDR / HBM)61
  • PCIe & CXL61
  • Embedded Peripherals (I2C / SPI / UART)61
  • High-Speed I/O (USB / Ethernet / MIPI)61
  • Protocol Verification & Compliance61
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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‹Handshake & Backpressure
  1. Topics
  2. Bus Protocols
  3. Protocol Fundamentals
  4. Handshake & Backpressure
  5. Handshake & Backpressure: Worked Example

Interface Protocols · All levels

Handshake & Backpressure: Worked Example

Worked Example for Handshake & Backpressure.

On this page

    Worked example

    Worked Example for Handshake & Backpressure focuses on ready deassertion rate, queue occupancy, throughput collapse point. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

    A product workload shows ready deassertion rate, queue occupancy, throughput collapse point. The first review mistake is to blame the whole interface. A better review starts by pinning one transaction, proving where protocol progress stopped, and checking whether the observed behavior is legal for Handshake & Backpressure.

    Sequence under inspection

    Diagram
    SEQUENCE — Handshake & Backpressure
    
      initiator            interconnect/PHY            target
          |  request (id) ------->  |                     |
          |                         |  forward ----------> |
          |                         |                     | work
          |                         |  <---- response ---- |
          |  <----- complete ------ |                     |
          |
       metric captured here: ready deassertion rate, queue occupancy, throughput collapse point

    VALID/READY handshake waveform

    Diagram
    VALID / READY HANDSHAKE (transfer happens when both are high)
    
    clk     _|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_|‾|_
    valid   ____|‾‾‾‾‾‾‾‾‾‾‾|________
    ready   ________|‾‾‾‾‾‾‾|____________
    xfer              ^   ^
                      |   |
           transfer on cycles where valid & ready are both 1
    
    Read rule:
      - valid must NOT wait for ready (no combinational deadlock)
      - data must stay stable while valid is high and ready is low
    1. Capture the failing waveform and transaction log.

    2. Tag the request ID, address, endpoint, or lane.

    3. Find the first response, retry, stall, or missing completion.

    4. Compare against waveform with stall windows, credit counter trace, FIFO occupancy graph.

    5. Choose one reversible fix and write the regression list before editing RTL or firmware.

    Did the fix work?

    Diagram
    BEFORE / AFTER — Handshake & Backpressure
    
               failing        target
    metric  |    ●              ┄┄┄┄┄┄┄
            |     \
            |      \___ ● bounded fix
            |           \
            |            ● validated
            +-------------------------------> change set
    Prove the mechanism moved the metric; one good dot is not proof.

    Protocol deep dive

    Before naming AXI or PCIe, engineers must master layering, handshakes, ordering, and bandwidth math. These four ideas explain 80% of integration bugs.

    Concept diagram

    Diagram
    FUNDAMENTALS STACK
    
    software intent
         |
    transaction (ID, addr, len, attr, order)
         |
    link/channel (handshake, credit, retry)
         |
    physical (clock, reset, lanes, PHY)
    
    Debug golden rule: never change layers without carrying transaction identity.

    Metric graph

    Diagram
    STALL BREAKDOWN EXAMPLE
    
    ready stalls      ████████████████  42%
    credit wait       ██████████        26%
    ordering block    ██████            16%
    reset/config      ████              10%
    other             ██                6%
    
    If ready stalls dominate, widening the bus will not help.

    Metrics and artifacts to collect

    • transaction latency by class

    • ready stall cycles

    • outstanding depth utilization

    • payload efficiency vs headline width

    • retry and error rate

    Mini case study

    A team widened a 64-bit interface to 128-bit but throughput rose only 8% because ready stalls from a slow slave dominated. Fixing slave acceptance and FIFO depth moved the metric; width did not.

    Debug branches

    • If latency spikes but bandwidth flat, check outstanding limits and ordering.

    • If throughput collapses at high load, draw the knee curve — you are past queue stability.

    • If intermittent, compare reset release order and clock domain boundaries.

    Senior review question

    Ask: what is the first transaction that deviates, and which spec rule does it test?

    Key takeaways

    • Connect every protocol claim to a transaction identity and measurable metric.

    • Store the artifact (waveform, log, counter) next to every signoff decision.

    Common pitfalls

    • Debugging timeouts without finding the first bad transaction.

    • Quoting peak bus width without payload efficiency and retry overhead.

    • Treating VIP compliance as a substitute for system integration replay.

    Narrative walkthrough

    A team sees ready deassertion rate, queue occupancy, throughput collapse point drop 40% after a seemingly small change near Handshake & Backpressure.

    They almost widen the interface. Instead they capture id=7 read burst and find W beats never matched AW len.

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    PreviousNext: Handshake & Backpressure: Pitfalls & Red Flags

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    See also

    • Handshake & Backpressure: Mechanism
    • Handshake & Backpressure: Inputs & Outputs
    • Handshake & Backpressure: Reports & Metrics