Interface Protocols · All levels

Ordering & Outstanding Rules: Interview Drills

Interview Drills for Ordering & Outstanding Rules.

Interview drills

Interview Drills for Ordering & Outstanding Rules focuses on reorder violation count, outstanding depth, completion latency spread. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

diagram

PROMPT
You see reorder violation count, outstanding depth, completion latency spread on Ordering & Outstanding Rules. Walk through root cause and fix.

STRONG ANSWER
1. Names the layer and transaction identity.
2. Explains IDs, tags, barriers, fences, and completion rules allow concurrency without breaking programmer-visible ordering.
3. Requests ID scoreboard, ordering matrix, litmus-style protocol sequence.
4. Proposes one reduced sequence and one system regression.

WEAK ANSWER
Jumps to widening the interface, increasing FIFO depth, or blaming firmware without evidence.

Diagram to draw on the whiteboard

Outstanding transactions timeline

diagram

OUTSTANDING = issued but not yet completed

issue   R1  R2  R3  R4
        |   |   |   |
time ---+---+---+---+----------------------->
resp            R1      R3  R2      R4
                ^^^^^^^^^^^^^^^^^^^^^^
   responses may return OUT OF ORDER across different IDs

Same ID  -> ordered
Diff ID  -> may reorder
Depth    -> how many can be in flight at once

Root-cause tree to narrate

diagram

ROOT-CAUSE TREE — Ordering & Outstanding Rules

reorder violation count, outstanding depth, completion latency spread looks wrong
        |
   reproducible?
     /        \
   no          yes
   |            |
 flaky env   same first transaction every time?
 / seed         /            \
              yes             no
               |               |
        protocol rule     timing/reset/PVT
        or config bug     or load-dependent

Protocol deep dive

Before naming AXI or PCIe, engineers must master layering, handshakes, ordering, and bandwidth math. These four ideas explain 80% of integration bugs.

Concept diagram

diagram

FUNDAMENTALS STACK

software intent
     |
transaction (ID, addr, len, attr, order)
     |
link/channel (handshake, credit, retry)
     |
physical (clock, reset, lanes, PHY)

Debug golden rule: never change layers without carrying transaction identity.

Metric graph

diagram

STALL BREAKDOWN EXAMPLE

ready stalls      ████████████████  42%
credit wait       ██████████        26%
ordering block    ██████            16%
reset/config      ████              10%
other             ██                6%

If ready stalls dominate, widening the bus will not help.

Metrics and artifacts to collect

transaction latency by class
ready stall cycles
outstanding depth utilization
payload efficiency vs headline width
retry and error rate

Mini case study

A team widened a 64-bit interface to 128-bit but throughput rose only 8% because ready stalls from a slow slave dominated. Fixing slave acceptance and FIFO depth moved the metric; width did not.

Debug branches

If latency spikes but bandwidth flat, check outstanding limits and ordering.
If throughput collapses at high load, draw the knee curve — you are past queue stability.
If intermittent, compare reset release order and clock domain boundaries.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.

Interview whiteboard

Draw layers first, then place the failing transaction on the diagram.

Practice this lesson