Interface Protocols · All levels

Layering & Transaction Model: Interview Drills

Interview Drills for Layering & Transaction Model.

Interview drills

Interview Drills for Layering & Transaction Model focuses on transaction latency, payload efficiency, retry rate. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

diagram

PROMPT
You see transaction latency, payload efficiency, retry rate on Layering & Transaction Model. Walk through root cause and fix.

STRONG ANSWER
1. Names the layer and transaction identity.
2. Explains PHY/link/transaction layering separates electrical transfer from ordering and software-visible semantics.
3. Requests protocol stack diagram, packet log, transaction trace, spec requirement table.
4. Proposes one reduced sequence and one system regression.

WEAK ANSWER
Jumps to widening the interface, increasing FIFO depth, or blaming firmware without evidence.

Diagram to draw on the whiteboard

Layered transaction model

diagram

LAYERED TRANSACTION MODEL

  +-------------------------------------------------------------+
  | Software / driver:  read(addr), write(addr,data), DMA start |
  +-------------------------------------------------------------+
                  | turns intent into a transaction
                  v
  +-------------------------------------------------------------+
  | Transaction layer: ID, address, length, attributes, order  |
  +-------------------------------------------------------------+
                  | maps transaction onto channel moves
                  v
  +-------------------------------------------------------------+
  | Link / channel: handshake, beats, credits, retries          |
  +-------------------------------------------------------------+
                  | serializes onto wires / lanes
                  v
  +-------------------------------------------------------------+
  | Physical / timing: clock, reset, pins, lanes, PHY training  |
  +-------------------------------------------------------------+

Rule: a bug at any layer is described using the layer ABOVE it as the symptom
and the layer BELOW it as the suspect.

Root-cause tree to narrate

diagram

ROOT-CAUSE TREE — Layering & Transaction Model

transaction latency, payload efficiency, retry rate looks wrong
        |
   reproducible?
     /        \
   no          yes
   |            |
 flaky env   same first transaction every time?
 / seed         /            \
              yes             no
               |               |
        protocol rule     timing/reset/PVT
        or config bug     or load-dependent

Protocol deep dive

Before naming AXI or PCIe, engineers must master layering, handshakes, ordering, and bandwidth math. These four ideas explain 80% of integration bugs.

Concept diagram

diagram

FUNDAMENTALS STACK

software intent
     |
transaction (ID, addr, len, attr, order)
     |
link/channel (handshake, credit, retry)
     |
physical (clock, reset, lanes, PHY)

Debug golden rule: never change layers without carrying transaction identity.

Metric graph

diagram

STALL BREAKDOWN EXAMPLE

ready stalls      ████████████████  42%
credit wait       ██████████        26%
ordering block    ██████            16%
reset/config      ████              10%
other             ██                6%

If ready stalls dominate, widening the bus will not help.

Metrics and artifacts to collect

transaction latency by class
ready stall cycles
outstanding depth utilization
payload efficiency vs headline width
retry and error rate

Mini case study

A team widened a 64-bit interface to 128-bit but throughput rose only 8% because ready stalls from a slow slave dominated. Fixing slave acceptance and FIFO depth moved the metric; width did not.

Debug branches

If latency spikes but bandwidth flat, check outstanding limits and ordering.
If throughput collapses at high load, draw the knee curve — you are past queue stability.
If intermittent, compare reset release order and clock domain boundaries.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.

Interview whiteboard

Draw layers first, then place the failing transaction on the diagram.

Practice this lesson