Interface Protocols · All levels
Bandwidth & Latency Budgeting: Interview Drills
Interview Drills for Bandwidth & Latency Budgeting.
Interview drills
Interview Drills for Bandwidth & Latency Budgeting focuses on sustained bandwidth, p99 latency, utilization, head-of-line blocking. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.
PROMPT
You see sustained bandwidth, p99 latency, utilization, head-of-line blocking on Bandwidth & Latency Budgeting. Walk through root cause and fix.
STRONG ANSWER
1. Names the layer and transaction identity.
2. Explains burst length, outstanding depth, arbitration, and packet overhead convert interface width into real workload throughput.
3. Requests bandwidth budget sheet, latency histogram, traffic replay summary.
4. Proposes one reduced sequence and one system regression.
WEAK ANSWER
Jumps to widening the interface, increasing FIFO depth, or blaming firmware without evidence.Diagram to draw on the whiteboard
Bandwidth vs offered load (knee curve)
LATENCY vs OFFERED LOAD
latency
^ *
| *
| *
| * <- knee: queues build fast
| * *
| * * * *
+--------------------------------------> offered load (% of peak)
0% 50% 80% 90% 100%
Lesson: usable bandwidth ends at the knee, not at 100% peak.Root-cause tree to narrate
ROOT-CAUSE TREE — Bandwidth & Latency Budgeting
sustained bandwidth, p99 latency, utilization, head-of-line blocking looks wrong
|
reproducible?
/ \
no yes
| |
flaky env same first transaction every time?
/ seed / \
yes no
| |
protocol rule timing/reset/PVT
or config bug or load-dependentProtocol deep dive
Before naming AXI or PCIe, engineers must master layering, handshakes, ordering, and bandwidth math. These four ideas explain 80% of integration bugs.
Concept diagram
FUNDAMENTALS STACK
software intent
|
transaction (ID, addr, len, attr, order)
|
link/channel (handshake, credit, retry)
|
physical (clock, reset, lanes, PHY)
Debug golden rule: never change layers without carrying transaction identity.Metric graph
STALL BREAKDOWN EXAMPLE
ready stalls ████████████████ 42%
credit wait ██████████ 26%
ordering block ██████ 16%
reset/config ████ 10%
other ██ 6%
If ready stalls dominate, widening the bus will not help.Metrics and artifacts to collect
transaction latency by class
ready stall cycles
outstanding depth utilization
payload efficiency vs headline width
retry and error rate
Mini case study
A team widened a 64-bit interface to 128-bit but throughput rose only 8% because ready stalls from a slow slave dominated. Fixing slave acceptance and FIFO depth moved the metric; width did not.
Debug branches
If latency spikes but bandwidth flat, check outstanding limits and ordering.
If throughput collapses at high load, draw the knee curve — you are past queue stability.
If intermittent, compare reset release order and clock domain boundaries.
Senior review question
Ask: what is the first transaction that deviates, and which spec rule does it test?
Key takeaways
Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.
Common pitfalls
Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.
Interview whiteboard
Draw layers first, then place the failing transaction on the diagram.