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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals61
    • Layering & Transaction Model
    • Handshake & Backpressure
    • Ordering & Outstanding Rules
    • Bandwidth & Latency Budgeting
      • Bandwidth & Latency Budgeting: Mechanism
      • Bandwidth & Latency Budgeting: Inputs & Outputs
      • Bandwidth & Latency Budgeting: Reports & Metrics
      • Bandwidth & Latency Budgeting: Debug Playbook
      • Bandwidth & Latency Budgeting: Worked Example
      • Bandwidth & Latency Budgeting: Pitfalls & Red Flags
      • Bandwidth & Latency Budgeting: Interview Drills
      • Bandwidth & Latency Budgeting: Review Checklist
      • Bandwidth & Latency Budgeting: Theory Deep Dive
      • Bandwidth & Latency Budgeting: Design Space
      • Bandwidth & Latency Budgeting: Expanded Case Study
      • Bandwidth & Latency Budgeting: Step-by-Step Walkthrough
      • Bandwidth & Latency Budgeting: Comparison Matrix
      • Bandwidth & Latency Budgeting: Software / Programmer View
      • Bandwidth & Latency Budgeting: Silicon PPA Impact
    • Protocol Fundamentals: Tricky Q&A
  • AMBA Family (APB / AHB / AXI)61
  • Coherence Fabrics (ACE / CHI)61
  • Memory Interfaces (DDR / LPDDR / HBM)61
  • PCIe & CXL61
  • Embedded Peripherals (I2C / SPI / UART)61
  • High-Speed I/O (USB / Ethernet / MIPI)61
  • Protocol Verification & Compliance61
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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‹Bandwidth & Latency Budgeting
  1. Topics
  2. Bus Protocols
  3. Protocol Fundamentals
  4. Bandwidth & Latency Budgeting
  5. Bandwidth & Latency Budgeting: Worked Example

Interface Protocols · All levels

Bandwidth & Latency Budgeting: Worked Example

Worked Example for Bandwidth & Latency Budgeting.

On this page

    Worked example

    Worked Example for Bandwidth & Latency Budgeting focuses on sustained bandwidth, p99 latency, utilization, head-of-line blocking. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

    A product workload shows sustained bandwidth, p99 latency, utilization, head-of-line blocking. The first review mistake is to blame the whole interface. A better review starts by pinning one transaction, proving where protocol progress stopped, and checking whether the observed behavior is legal for Bandwidth & Latency Budgeting.

    Sequence under inspection

    Diagram
    SEQUENCE — Bandwidth & Latency Budgeting
    
      initiator            interconnect/PHY            target
          |  request (id) ------->  |                     |
          |                         |  forward ----------> |
          |                         |                     | work
          |                         |  <---- response ---- |
          |  <----- complete ------ |                     |
          |
       metric captured here: sustained bandwidth, p99 latency, utilization, head-of-line blocking

    Bandwidth vs offered load (knee curve)

    Diagram
    LATENCY vs OFFERED LOAD
    
    latency
      ^                                   *
      |                                 *
      |                              *
      |                          *  <- knee: queues build fast
      |                  *  *
      |   *  *  *  *
      +--------------------------------------> offered load (% of peak)
       0%        50%        80%   90%  100%
    
    Lesson: usable bandwidth ends at the knee, not at 100% peak.
    1. Capture the failing waveform and transaction log.

    2. Tag the request ID, address, endpoint, or lane.

    3. Find the first response, retry, stall, or missing completion.

    4. Compare against bandwidth budget sheet, latency histogram, traffic replay summary.

    5. Choose one reversible fix and write the regression list before editing RTL or firmware.

    Did the fix work?

    Diagram
    BEFORE / AFTER — Bandwidth & Latency Budgeting
    
               failing        target
    metric  |    ●              ┄┄┄┄┄┄┄
            |     \
            |      \___ ● bounded fix
            |           \
            |            ● validated
            +-------------------------------> change set
    Prove the mechanism moved the metric; one good dot is not proof.

    Protocol deep dive

    Before naming AXI or PCIe, engineers must master layering, handshakes, ordering, and bandwidth math. These four ideas explain 80% of integration bugs.

    Concept diagram

    Diagram
    FUNDAMENTALS STACK
    
    software intent
         |
    transaction (ID, addr, len, attr, order)
         |
    link/channel (handshake, credit, retry)
         |
    physical (clock, reset, lanes, PHY)
    
    Debug golden rule: never change layers without carrying transaction identity.

    Metric graph

    Diagram
    STALL BREAKDOWN EXAMPLE
    
    ready stalls      ████████████████  42%
    credit wait       ██████████        26%
    ordering block    ██████            16%
    reset/config      ████              10%
    other             ██                6%
    
    If ready stalls dominate, widening the bus will not help.

    Metrics and artifacts to collect

    • transaction latency by class

    • ready stall cycles

    • outstanding depth utilization

    • payload efficiency vs headline width

    • retry and error rate

    Mini case study

    A team widened a 64-bit interface to 128-bit but throughput rose only 8% because ready stalls from a slow slave dominated. Fixing slave acceptance and FIFO depth moved the metric; width did not.

    Debug branches

    • If latency spikes but bandwidth flat, check outstanding limits and ordering.

    • If throughput collapses at high load, draw the knee curve — you are past queue stability.

    • If intermittent, compare reset release order and clock domain boundaries.

    Senior review question

    Ask: what is the first transaction that deviates, and which spec rule does it test?

    Key takeaways

    • Connect every protocol claim to a transaction identity and measurable metric.

    • Store the artifact (waveform, log, counter) next to every signoff decision.

    Common pitfalls

    • Debugging timeouts without finding the first bad transaction.

    • Quoting peak bus width without payload efficiency and retry overhead.

    • Treating VIP compliance as a substitute for system integration replay.

    Narrative walkthrough

    A team sees sustained bandwidth, p99 latency, utilization, head-of-line blocking drop 40% after a seemingly small change near Bandwidth & Latency Budgeting.

    They almost widen the interface. Instead they capture id=7 read burst and find W beats never matched AW len.

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    PreviousNext: Bandwidth & Latency Budgeting: Pitfalls & Red Flags

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    See also

    • Bandwidth & Latency Budgeting: Mechanism
    • Bandwidth & Latency Budgeting: Inputs & Outputs
    • Bandwidth & Latency Budgeting: Reports & Metrics