Bandwidth & Latency Budgeting: Mechanism

Mechanism to understand

Mechanism for Bandwidth & Latency Budgeting focuses on sustained bandwidth, p99 latency, utilization, head-of-line blocking. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

burst length, outstanding depth, arbitration, and packet overhead convert interface width into real workload throughput. Think of it as a contract enforced at boundaries: the sender promises stability and legality, the receiver promises forward progress, and the fabric in between promises not to silently change identity or ordering.

• Identify the transaction boundary: request, data, response, completion, or retry.

• Identify the flow-control boundary: valid/ready, grant, credit, FIFO depth, or lane state.

• Identify what the receiver is allowed to assume and what the sender must hold stable.

Layered view

PROTOCOL STACK VIEW — Bandwidth & Latency Budgeting

software / firmware intent
        |
        v
transaction semantics: address, ID, length, attributes, ordering
        |
        v
link / channel behavior: handshake, credits, backpressure, retries
        |
        v
physical or timing layer: clocking, reset, pins, lanes, PHY
        |
        v
observability: waveform, VIP transaction, counter, analyzer trace

Debug rule: never jump layers without carrying the transaction identity with you.

Bandwidth vs offered load (knee curve)

LATENCY vs OFFERED LOAD

latency
  ^                                   *
  |                                 *
  |                              *
  |                          *  <- knee: queues build fast
  |                  *  *
  |   *  *  *  *
  +--------------------------------------> offered load (% of peak)
   0%        50%        80%   90%  100%

Lesson: usable bandwidth ends at the knee, not at 100% peak.

Payload efficiency stack

WHERE HEADLINE BANDWIDTH GOES

raw link            ████████████████████████  100%
- protocol overhead ██████████████████████    ~92%
- turnaround/idle   ██████████████████        ~75%
- retries/refresh   ████████████████          ~66%
= useful payload    ████████████████          ~66%

Always quote the bottom bar, not the top bar.

Layer responsibilities

LAYER RESPONSIBILITY — Bandwidth & Latency Budgeting

layer          owns                         common failure
-----------    --------------------------   -----------------------
software       intent, ordering needs       wrong assumption
transaction    id/addr/len/attributes       ordering / outstanding
link/channel   handshake, credits, retry    backpressure / deadlock
physical       clock/reset/lanes/PHY        timing / training / SI
observability  waveform/log/counter         missing evidence

Protocol deep dive

Before naming AXI or PCIe, engineers must master layering, handshakes, ordering, and bandwidth math. These four ideas explain 80% of integration bugs.

Concept diagram

FUNDAMENTALS STACK

software intent
     |
transaction (ID, addr, len, attr, order)
     |
link/channel (handshake, credit, retry)
     |
physical (clock, reset, lanes, PHY)

Debug golden rule: never change layers without carrying transaction identity.

Metric graph

STALL BREAKDOWN EXAMPLE

ready stalls      ████████████████  42%
credit wait       ██████████        26%
ordering block    ██████            16%
reset/config      ████              10%
other             ██                6%

If ready stalls dominate, widening the bus will not help.

Metrics and artifacts to collect

• transaction latency by class

• ready stall cycles

• outstanding depth utilization

• payload efficiency vs headline width

• retry and error rate

Mini case study

A team widened a 64-bit interface to 128-bit but throughput rose only 8% because ready stalls from a slow slave dominated. Fixing slave acceptance and FIFO depth moved the metric; width did not.

Debug branches

• If latency spikes but bandwidth flat, check outstanding limits and ordering.

• If throughput collapses at high load, draw the knee curve — you are past queue stability.

• If intermittent, compare reset release order and clock domain boundaries.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.

Mechanism deep dive

burst length, outstanding depth, arbitration, and packet overhead convert interface width into real workload throughput.

Walk the transaction forward: request accepted → data moves → response completes → software visible effect.