AXI-Lite & AXI-Stream: Software / Programmer View

Software and programmer view

Drivers depend on address map, interrupt timing, and DMA descriptor contracts.

What programmers feel

• Timeouts with healthy-looking hardware counters

• Data corruption without obvious ECC/CRC

• Ordering surprises under multi-threaded drivers

• Performance cliffs when payload size changes

API / driver implications

• Descriptor alignment and cache line sharing

• Fence/barrier placement around DMA

• IRQ type (level vs edge) and clear sequence

• Memory-mapped register access ordering

Compiler and runtime interaction

• Volatile and barrier semantics for device memory

• Struct padding affecting burst efficiency

• Batching policy in userspace drivers

Software-side mitigations

• Pad structures to cache lines

• Pin buffers and use coherent DMA where required

• Expose hardware counters to software profilers

• Document legal outstanding depth and ordering

SOFTWARE EXAMPLE — AXI-Lite & AXI-Stream

// Bad: assumes ordering across unrelated IDs without fence
dma_start(ch0); dma_start(ch1); cpu_read(result); // may see stale

// Better: document which completions are ordered and insert barrier
dma_start(ch0); wait_completion(ch0); cpu_read(result);

Layer the driver touches

LAYER RESPONSIBILITY — AXI-Lite & AXI-Stream

layer          owns                         common failure
-----------    --------------------------   -----------------------
software       intent, ordering needs       wrong assumption
transaction    id/addr/len/attributes       ordering / outstanding
link/channel   handshake, credits, retry    backpressure / deadlock
physical       clock/reset/lanes/PHY        timing / training / SI
observability  waveform/log/counter         missing evidence

Protocol deep dive

AMBA is the on-chip lingua franca: APB for control, AHB for legacy bursts, AXI for high-performance coherent fabrics.

Concept diagram

AMBA INTEGRATION MAP

CPU --AXI--> NIC --AXI--> SRAM
  |              |
  +--AXI-Lite--> peripherals (GPIO, timers)
  +--AXI-Stream-> video pipe

Every bridge is a contract rewrite: width, ID, burst, cache attrs.

Metric graph

AXI CHANNEL ACTIVITY (mixed traffic)

AW+W     ████████████
AR       ████████████████
R        ██████████████
B        ████████

Read-heavy phase: AR/R dominate; write resp may look idle while system is healthy.

Metrics and artifacts to collect

• AR/AW/R/B channel utilization

• write resp latency

• read OSTD depth

• SLVERR/DECERR count

• bridge hang log

Mini case study

Write burst hung because W beats arrived before AW for a narrow bridge that reordered channels. VIP flagged nothing until full-system traffic interleaved reads and writes.

Debug branches

• Hung write: verify AW/W ordering and wlast alignment.

• Hung read: check arready stall and rlast per ID.

• Decode errors: address map vs interconnect route table.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.

Principal review addendum

Re-read AXI-Lite & AXI-Stream against one concrete product workload, not a synthetic directed test.

AXI-Lite removes bursts for control paths while AXI-Stream moves ordered data without addresses.