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APB & AHB Basics: Reports & Metrics

Reports & Metrics for APB & AHB Basics.

Reports and metrics

Reports & Metrics for APB & AHB Basics focuses on register access latency, bus utilization, wait-state rate. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

The job of a report is to turn register access latency, bus utilization, wait-state rate into a decision. A single average number is almost never enough; you need the distribution, the traffic class breakdown, and a clear gap between legal maximum and product target.

Metric movement

diagram

METRIC GRAPH — register access latency, bus utilization, wait-state rate

throughput / success
  ^
  |                         target
  |                       - - - - - - -
  |                  o after bounded fix
  |              o
  |         o baseline
  |    o failing run
  +--------------------------------------> experiment
    config A     isolated root cause     accepted change

Readout:
  - compare identical payload, clock, reset, traffic seed, and firmware setup
  - separate headline bandwidth from useful payload bandwidth
  - explain why the protocol mechanism moved the metric

Latency distribution

diagram

LATENCY HISTOGRAM — APB & AHB Basics

count
  |               ███
  |             ███████
  |          █████████████
  |        █████████████████        <- long tail = the real complaint
  |      ████████████████████████████
  +------------------------------------> latency
   p50      p90    p95       p99  (watch p99, not the average)

Average hides the tail; product pain lives at p95/p99.

Track register access latency, bus utilization, wait-state rate by traffic class, payload size, and clock/reset mode.
Report p50/p95/p99 latency when user-visible stalls matter.
Include legal maximums and product targets; they are not the same thing.
Always store the metric next to the artifact that produced it.

Protocol deep dive

AMBA is the on-chip lingua franca: APB for control, AHB for legacy bursts, AXI for high-performance coherent fabrics.

Concept diagram

diagram

AMBA INTEGRATION MAP

CPU --AXI--> NIC --AXI--> SRAM
  |              |
  +--AXI-Lite--> peripherals (GPIO, timers)
  +--AXI-Stream-> video pipe

Every bridge is a contract rewrite: width, ID, burst, cache attrs.

Metric graph

diagram

AXI CHANNEL ACTIVITY (mixed traffic)

AW+W     ████████████
AR       ████████████████
R        ██████████████
B        ████████

Read-heavy phase: AR/R dominate; write resp may look idle while system is healthy.

Metrics and artifacts to collect

AR/AW/R/B channel utilization
write resp latency
read OSTD depth
SLVERR/DECERR count
bridge hang log

Mini case study

Write burst hung because W beats arrived before AW for a narrow bridge that reordered channels. VIP flagged nothing until full-system traffic interleaved reads and writes.

Debug branches

Hung write: verify AW/W ordering and wlast alignment.
Hung read: check arready stall and rlast per ID.
Decode errors: address map vs interconnect route table.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.

How to read the numbers

Practice this lesson