APB & AHB Basics: Interview Drills

PROMPT
You see register access latency, bus utilization, wait-state rate on APB & AHB Basics. Walk through root cause and fix.

STRONG ANSWER
1. Names the layer and transaction identity.
2. Explains APB optimizes simple register transactions while AHB supports pipelined bus transfers and burst access.
3. Requests bus timing waveform, address decode table, bridge transaction log.
4. Proposes one reduced sequence and one system regression.

WEAK ANSWER
Jumps to widening the interface, increasing FIFO depth, or blaming firmware without evidence.

APB STATE MACHINE

   IDLE --(transfer)--> SETUP --(always)--> ACCESS
    ^                                          |
    |                                          |
    +----------(pready=1, no more)-------------+
                       |
                 (pready=1, more) --> SETUP

SETUP : psel=1, penable=0
ACCESS: psel=1, penable=1, wait while pready=0

ROOT-CAUSE TREE — APB & AHB Basics

register access latency, bus utilization, wait-state rate looks wrong
        |
   reproducible?
     /        \
   no          yes
   |            |
 flaky env   same first transaction every time?
 / seed         /            \
              yes             no
               |               |
        protocol rule     timing/reset/PVT
        or config bug     or load-dependent

AMBA INTEGRATION MAP

CPU --AXI--> NIC --AXI--> SRAM
  |              |
  +--AXI-Lite--> peripherals (GPIO, timers)
  +--AXI-Stream-> video pipe

Every bridge is a contract rewrite: width, ID, burst, cache attrs.

AXI CHANNEL ACTIVITY (mixed traffic)

AW+W     ████████████
AR       ████████████████
R        ██████████████
B        ████████

Read-heavy phase: AR/R dominate; write resp may look idle while system is healthy.