Interface Protocols · All levels

AXI Channels & Transfers: Interview Drills

Interview Drills for AXI Channels & Transfers.

Interview drills

Interview Drills for AXI Channels & Transfers focuses on read/write throughput, outstanding transaction depth, response error rate. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

diagram

PROMPT
You see read/write throughput, outstanding transaction depth, response error rate on AXI Channels & Transfers. Walk through root cause and fix.

STRONG ANSWER
1. Names the layer and transaction identity.
2. Explains AXI splits address, data, and response channels so reads and writes can progress independently.
3. Requests AR/AW/W/R/B channel waveform, ID scoreboard, burst decode report.
4. Proposes one reduced sequence and one system regression.

WEAK ANSWER
Jumps to widening the interface, increasing FIFO depth, or blaming firmware without evidence.

Diagram to draw on the whiteboard

Five independent AXI channels

diagram

AXI CHANNELS (each is its own valid/ready handshake)

WRITE:  AW (addr) ─┐
        W  (data) ─┼─> slave ──> B (resp)
READ:   AR (addr) ───> slave ──> R (data+resp)

Independence is the point:
  - reads and writes progress in parallel
  - address can be sent before data is ready (within rules)

Root-cause tree to narrate

diagram

ROOT-CAUSE TREE — AXI Channels & Transfers

read/write throughput, outstanding transaction depth, response error rate looks wrong
        |
   reproducible?
     /        \
   no          yes
   |            |
 flaky env   same first transaction every time?
 / seed         /            \
              yes             no
               |               |
        protocol rule     timing/reset/PVT
        or config bug     or load-dependent

Protocol deep dive

AMBA is the on-chip lingua franca: APB for control, AHB for legacy bursts, AXI for high-performance coherent fabrics.

Concept diagram

diagram

AMBA INTEGRATION MAP

CPU --AXI--> NIC --AXI--> SRAM
  |              |
  +--AXI-Lite--> peripherals (GPIO, timers)
  +--AXI-Stream-> video pipe

Every bridge is a contract rewrite: width, ID, burst, cache attrs.

Metric graph

diagram

AXI CHANNEL ACTIVITY (mixed traffic)

AW+W     ████████████
AR       ████████████████
R        ██████████████
B        ████████

Read-heavy phase: AR/R dominate; write resp may look idle while system is healthy.

Metrics and artifacts to collect

AR/AW/R/B channel utilization
write resp latency
read OSTD depth
SLVERR/DECERR count
bridge hang log

Mini case study

Write burst hung because W beats arrived before AW for a narrow bridge that reordered channels. VIP flagged nothing until full-system traffic interleaved reads and writes.

Debug branches

Hung write: verify AW/W ordering and wlast alignment.
Hung read: check arready stall and rlast per ID.
Decode errors: address map vs interconnect route table.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.

Interview whiteboard

Draw layers first, then place the failing transaction on the diagram.

Practice this lesson