PROMPT
You see read/write throughput, outstanding transaction depth, response error rate on AXI Channels & Transfers. Walk through root cause and fix.

STRONG ANSWER
1. Names the layer and transaction identity.
2. Explains AXI splits address, data, and response channels so reads and writes can progress independently.
3. Requests AR/AW/W/R/B channel waveform, ID scoreboard, burst decode report.
4. Proposes one reduced sequence and one system regression.

WEAK ANSWER
Jumps to widening the interface, increasing FIFO depth, or blaming firmware without evidence.

AXI CHANNELS (each is its own valid/ready handshake)

WRITE:  AW (addr) ─┐
        W  (data) ─┼─> slave ──> B (resp)
READ:   AR (addr) ───> slave ──> R (data+resp)

Independence is the point:
  - reads and writes progress in parallel
  - address can be sent before data is ready (within rules)

ROOT-CAUSE TREE — AXI Channels & Transfers

read/write throughput, outstanding transaction depth, response error rate looks wrong
        |
   reproducible?
     /        \
   no          yes
   |            |
 flaky env   same first transaction every time?
 / seed         /            \
              yes             no
               |               |
        protocol rule     timing/reset/PVT
        or config bug     or load-dependent

AMBA INTEGRATION MAP

CPU --AXI--> NIC --AXI--> SRAM
  |              |
  +--AXI-Lite--> peripherals (GPIO, timers)
  +--AXI-Stream-> video pipe

Every bridge is a contract rewrite: width, ID, burst, cache attrs.

AXI CHANNEL ACTIVITY (mixed traffic)

AW+W     ████████████
AR       ████████████████
R        ██████████████
B        ████████

Read-heavy phase: AR/R dominate; write resp may look idle while system is healthy.