AXI Channels & Transfers: Worked Example

Worked example

Worked Example for AXI Channels & Transfers focuses on read/write throughput, outstanding transaction depth, response error rate. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

A product workload shows read/write throughput, outstanding transaction depth, response error rate. The first review mistake is to blame the whole interface. A better review starts by pinning one transaction, proving where protocol progress stopped, and checking whether the observed behavior is legal for AXI Channels & Transfers.

Sequence under inspection

SEQUENCE — AXI Channels & Transfers

  initiator            interconnect/PHY            target
      |  request (id) ------->  |                     |
      |                         |  forward ----------> |
      |                         |                     | work
      |                         |  <---- response ---- |
      |  <----- complete ------ |                     |
      |
   metric captured here: read/write throughput, outstanding transaction depth, response error rate

Five independent AXI channels

AXI CHANNELS (each is its own valid/ready handshake)

WRITE:  AW (addr) ─┐
        W  (data) ─┼─> slave ──> B (resp)
READ:   AR (addr) ───> slave ──> R (data+resp)

Independence is the point:
  - reads and writes progress in parallel
  - address can be sent before data is ready (within rules)

1. Capture the failing waveform and transaction log.

2. Tag the request ID, address, endpoint, or lane.

3. Find the first response, retry, stall, or missing completion.

4. Compare against AR/AW/W/R/B channel waveform, ID scoreboard, burst decode report.

5. Choose one reversible fix and write the regression list before editing RTL or firmware.

Did the fix work?

BEFORE / AFTER — AXI Channels & Transfers

           failing        target
metric  |    ●              ┄┄┄┄┄┄┄
        |     \
        |      \___ ● bounded fix
        |           \
        |            ● validated
        +-------------------------------> change set
Prove the mechanism moved the metric; one good dot is not proof.

Protocol deep dive

AMBA is the on-chip lingua franca: APB for control, AHB for legacy bursts, AXI for high-performance coherent fabrics.

Concept diagram

AMBA INTEGRATION MAP

CPU --AXI--> NIC --AXI--> SRAM
  |              |
  +--AXI-Lite--> peripherals (GPIO, timers)
  +--AXI-Stream-> video pipe

Every bridge is a contract rewrite: width, ID, burst, cache attrs.

Metric graph

AXI CHANNEL ACTIVITY (mixed traffic)

AW+W     ████████████
AR       ████████████████
R        ██████████████
B        ████████

Read-heavy phase: AR/R dominate; write resp may look idle while system is healthy.

Metrics and artifacts to collect

• AR/AW/R/B channel utilization

• write resp latency

• read OSTD depth

• SLVERR/DECERR count

• bridge hang log

Mini case study

Write burst hung because W beats arrived before AW for a narrow bridge that reordered channels. VIP flagged nothing until full-system traffic interleaved reads and writes.

Debug branches

• Hung write: verify AW/W ordering and wlast alignment.

• Hung read: check arready stall and rlast per ID.

• Decode errors: address map vs interconnect route table.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.

Narrative walkthrough

A team sees read/write throughput, outstanding transaction depth, response error rate drop 40% after a seemingly small change near AXI Channels & Transfers.

They almost widen the interface. Instead they capture id=7 read burst and find W beats never matched AW len.