CXL Attach Modes: Software / Programmer View

Software and programmer view

Enumeration, BAR assignment, and CXL mode setup are firmware-owned protocol steps.

What programmers feel

• Timeouts with healthy-looking hardware counters

• Data corruption without obvious ECC/CRC

• Ordering surprises under multi-threaded drivers

• Performance cliffs when payload size changes

API / driver implications

• Descriptor alignment and cache line sharing

• Fence/barrier placement around DMA

• IRQ type (level vs edge) and clear sequence

• Memory-mapped register access ordering

Compiler and runtime interaction

• Volatile and barrier semantics for device memory

• Struct padding affecting burst efficiency

• Batching policy in userspace drivers

Software-side mitigations

• Pad structures to cache lines

• Pin buffers and use coherent DMA where required

• Expose hardware counters to software profilers

• Document legal outstanding depth and ordering

SOFTWARE EXAMPLE — CXL Attach Modes

// Bad: assumes ordering across unrelated IDs without fence
dma_start(ch0); dma_start(ch1); cpu_read(result); // may see stale

// Better: document which completions are ordered and insert barrier
dma_start(ch0); wait_completion(ch0); cpu_read(result);

Layer the driver touches

LAYER RESPONSIBILITY — CXL Attach Modes

layer          owns                         common failure
-----------    --------------------------   -----------------------
software       intent, ordering needs       wrong assumption
transaction    id/addr/len/attributes       ordering / outstanding
link/channel   handshake, credits, retry    backpressure / deadlock
physical       clock/reset/lanes/PHY        timing / training / SI
observability  waveform/log/counter         missing evidence

Protocol deep dive

PCIe is reliable packet delivery over unreliable links; debug flows PHY -> DLL -> TLP -> firmware.

Concept diagram

PCIe DEBUG TOP-DOWN

L0 link healthy?  -> credits OK?  -> TLP completes?  -> driver happy?

Skip a layer and you will mis-own the bug.

Metric graph

LINK DEGRADE EXAMPLE

target x4 Gen4  ---- ---- ---- ----
actual   x4 Gen4  ---- ---- ---- ----   (eval board)
actual   x1 Gen3  -                   (product board)

Package/SI often shows up as width downgrade, not hard fail.

Metrics and artifacts to collect

• link width/speed

• replay count

• completion timeout

• AER error log

• LTSSM history

Mini case study

Endpoint enumerated but DMA timed out: completion credits exhausted because a switch port was misconfigured in firmware, not because the endpoint was broken.

Debug branches

• If degrade at width/speed, PHY/SI before driver.

• If replay storm, link layer before transaction layer.

• If CXL coherency bug, separate .io vs .cache vs .mem traffic.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.

Principal review addendum

Re-read CXL Attach Modes against one concrete product workload, not a synthetic directed test.

CXL.io, CXL.cache, and CXL.mem layer coherent and memory semantics on PCIe infrastructure.