Use these drills after completing all topics in PCIe & CXL. Answer with layer, transaction, metric, artifact, and regression.
[INT][PROT][PCIE-CXL]
Q: What do PCIe credits control?
A:
How many TLPs of each type the sender may issue based on receiver buffer space.
FOLLOW-UP TRAP: Confusing credits with link width.[INT][PROT][PCIE-CXL]
Q: LTSSM reached L0 but width is wrong — what next?
A:
PHY/SI/lane margin and package; read LTSSM history and margin reports.
FOLLOW-UP TRAP: Blaming enumeration software first.[INT][PROT][PCIE-CXL]
Q: CXL.cache vs CXL.mem — difference?
A:
.cache is coherent caching of host memory; .mem is device-attached memory mapped to host.
FOLLOW-UP TRAP: Treating all CXL as PCIe DMA.LAYER -> TRANSACTION -> METRIC -> ARTIFACT -> FIX -> REGRESSIONPCIe DEBUG TOP-DOWN
L0 link healthy? -> credits OK? -> TLP completes? -> driver happy?
Skip a layer and you will mis-own the bug.If degrade at width/speed, PHY/SI before driver.
If replay storm, link layer before transaction layer.
If CXL coherency bug, separate .io vs .cache vs .mem traffic.
Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.
Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.