PCIe & CXL: Tricky Q&A

Section Q&A bank

Use these drills after completing all topics in PCIe & CXL. Answer with layer, transaction, metric, artifact, and regression.

What do PCIe credits control?

[INT][PROT][PCIE-CXL]

Q: What do PCIe credits control?

A:
How many TLPs of each type the sender may issue based on receiver buffer space.

FOLLOW-UP TRAP: Confusing credits with link width.

LTSSM reached L0 but width is wrong — what next?

[INT][PROT][PCIE-CXL]

Q: LTSSM reached L0 but width is wrong — what next?

A:
PHY/SI/lane margin and package; read LTSSM history and margin reports.

FOLLOW-UP TRAP: Blaming enumeration software first.

CXL.cache vs CXL.mem — difference?

[INT][PROT][PCIE-CXL]

Q: CXL.cache vs CXL.mem — difference?

A:
.cache is coherent caching of host memory; .mem is device-attached memory mapped to host.

FOLLOW-UP TRAP: Treating all CXL as PCIe DMA.

Q&A drill guide

LAYER -> TRANSACTION -> METRIC -> ARTIFACT -> FIX -> REGRESSION

Sketch while answering

PCIe DEBUG TOP-DOWN

L0 link healthy?  -> credits OK?  -> TLP completes?  -> driver happy?

Skip a layer and you will mis-own the bug.

Common traps

• If degrade at width/speed, PHY/SI before driver.

• If replay storm, link layer before transaction layer.

• If CXL coherency bug, separate .io vs .cache vs .mem traffic.

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.