CXL Attach Modes

What this topic teaches

CXL Attach Modes is about converting a protocol rule into a measurable silicon contract. CXL.io, CXL.cache, and CXL.mem layer coherent and memory semantics on PCIe infrastructure. The hard part is never the happy-path diagram; it is proving, under real traffic, which layer and which transaction broke the contract.

The senior-engineer question

When cache/memory latency, coherency traffic, attach-mode bandwidth moves, can you identify the transaction, the protocol layer, the responsible owner, and the smallest experiment that proves the root cause?

PROTOCOL STACK VIEW — CXL Attach Modes

software / firmware intent
        |
        v
transaction semantics: address, ID, length, attributes, ordering
        |
        v
link / channel behavior: handshake, credits, backpressure, retries
        |
        v
physical or timing layer: clocking, reset, pins, lanes, PHY
        |
        v
observability: waveform, VIP transaction, counter, analyzer trace

Debug rule: never jump layers without carrying the transaction identity with you.

Picture the protocol

Start every study session by drawing the behavior before reading signals. The diagrams below are the mental models to reproduce on a whiteboard.

CXL.io / CXL.cache / CXL.mem

CXL SUB-PROTOCOLS (share PCIe PHY)

CXL.io   : PCIe-like discovery, config, DMA            (Type 1/2/3)
CXL.cache: device caches host memory coherently        (Type 1/2)
CXL.mem  : host accesses device-attached memory         (Type 2/3)

Type 3 example: memory expander = mostly CXL.mem + CXL.io.

Transaction sequence

SEQUENCE — CXL Attach Modes

  initiator            interconnect/PHY            target
      |  request (id) ------->  |                     |
      |                         |  forward ----------> |
      |                         |                     | work
      |                         |  <---- response ---- |
      |  <----- complete ------ |                     |
      |
   metric captured here: cache/memory latency, coherency traffic, attach-mode bandwidth

Who owns which layer

LAYER RESPONSIBILITY — CXL Attach Modes

layer          owns                         common failure
-----------    --------------------------   -----------------------
software       intent, ordering needs       wrong assumption
transaction    id/addr/len/attributes       ordering / outstanding
link/channel   handshake, credits, retry    backpressure / deadlock
physical       clock/reset/lanes/PHY        timing / training / SI
observability  waveform/log/counter         missing evidence

Evidence to collect

• Primary metric: cache/memory latency, coherency traffic, attach-mode bandwidth.

• Primary artifact: CXL mode table, coherency trace, memory window map.

• Owners to bring into review: system architect, CXL controller owner, software owner.

• Spec clause or requirement ID for every claim.

• One traffic replay that fails and one reduced sequence that isolates the rule.

Ownership map

OWNERSHIP MAP — CXL Attach Modes

evidence type        owner who reads it
-----------------    ---------------------------
waveform/RTL        system architect
spec/VIP            CXL controller owner
firmware/system     software owner

Rule: every metric must have a named owner before a review starts.

Subpages in this topic

Each topic is taught across mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon PPA impact.

Key takeaways

• Carry transaction identity across waveform, log, counter, and spec view.

• Separate protocol violation, integration configuration, and performance bottleneck before proposing a fix.

• Draw the diagram first; the waveform should confirm the picture, not replace it.

Common pitfalls

• Debugging only one channel or layer.

• Treating a VIP error message as root cause instead of evidence.

• Quoting peak interface bandwidth without payload efficiency.

Protocol deep dive

PCIe is reliable packet delivery over unreliable links; debug flows PHY -> DLL -> TLP -> firmware.

Concept diagram

PCIe DEBUG TOP-DOWN

L0 link healthy?  -> credits OK?  -> TLP completes?  -> driver happy?

Skip a layer and you will mis-own the bug.

Metric graph

LINK DEGRADE EXAMPLE

target x4 Gen4  ---- ---- ---- ----
actual   x4 Gen4  ---- ---- ---- ----   (eval board)
actual   x1 Gen3  -                   (product board)

Package/SI often shows up as width downgrade, not hard fail.

Metrics and artifacts to collect

• link width/speed

• replay count

• completion timeout

• AER error log

• LTSSM history

Mini case study

Endpoint enumerated but DMA timed out: completion credits exhausted because a switch port was misconfigured in firmware, not because the endpoint was broken.

Debug branches

• If degrade at width/speed, PHY/SI before driver.

• If replay storm, link layer before transaction layer.

• If CXL coherency bug, separate .io vs .cache vs .mem traffic.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.