Mechanism to understand

Mechanism for CXL Attach Modes focuses on cache/memory latency, coherency traffic, attach-mode bandwidth. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

CXL.io, CXL.cache, and CXL.mem layer coherent and memory semantics on PCIe infrastructure. Think of it as a contract enforced at boundaries: the sender promises stability and legality, the receiver promises forward progress, and the fabric in between promises not to silently change identity or ordering.

• Identify the transaction boundary: request, data, response, completion, or retry.

• Identify the flow-control boundary: valid/ready, grant, credit, FIFO depth, or lane state.

• Identify what the receiver is allowed to assume and what the sender must hold stable.

Layered view

PROTOCOL STACK VIEW — CXL Attach Modes

software / firmware intent
        |
        v
transaction semantics: address, ID, length, attributes, ordering
        |
        v
link / channel behavior: handshake, credits, backpressure, retries
        |
        v
physical or timing layer: clocking, reset, pins, lanes, PHY
        |
        v
observability: waveform, VIP transaction, counter, analyzer trace

Debug rule: never jump layers without carrying the transaction identity with you.

CXL.io / CXL.cache / CXL.mem

CXL SUB-PROTOCOLS (share PCIe PHY)

CXL.io   : PCIe-like discovery, config, DMA            (Type 1/2/3)
CXL.cache: device caches host memory coherently        (Type 1/2)
CXL.mem  : host accesses device-attached memory         (Type 2/3)

Type 3 example: memory expander = mostly CXL.mem + CXL.io.

Layer responsibilities

LAYER RESPONSIBILITY — CXL Attach Modes

layer          owns                         common failure
-----------    --------------------------   -----------------------
software       intent, ordering needs       wrong assumption
transaction    id/addr/len/attributes       ordering / outstanding
link/channel   handshake, credits, retry    backpressure / deadlock
physical       clock/reset/lanes/PHY        timing / training / SI
observability  waveform/log/counter         missing evidence

Protocol deep dive

PCIe is reliable packet delivery over unreliable links; debug flows PHY -> DLL -> TLP -> firmware.

Concept diagram

PCIe DEBUG TOP-DOWN

L0 link healthy?  -> credits OK?  -> TLP completes?  -> driver happy?

Skip a layer and you will mis-own the bug.

Metric graph

LINK DEGRADE EXAMPLE

target x4 Gen4  ---- ---- ---- ----
actual   x4 Gen4  ---- ---- ---- ----   (eval board)
actual   x1 Gen3  -                   (product board)

Package/SI often shows up as width downgrade, not hard fail.

Metrics and artifacts to collect

• link width/speed

• replay count

• completion timeout

• AER error log

• LTSSM history

Mini case study

Endpoint enumerated but DMA timed out: completion credits exhausted because a switch port was misconfigured in firmware, not because the endpoint was broken.

Debug branches

• If degrade at width/speed, PHY/SI before driver.

• If replay storm, link layer before transaction layer.

• If CXL coherency bug, separate .io vs .cache vs .mem traffic.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.

Mechanism deep dive

CXL.io, CXL.cache, and CXL.mem layer coherent and memory semantics on PCIe infrastructure.

Walk the transaction forward: request accepted → data moves → response completes → software visible effect.