Interface Protocols · All levels

CXL Attach Modes: Interview Drills

Interview Drills for CXL Attach Modes.

Interview drills

Interview Drills for CXL Attach Modes focuses on cache/memory latency, coherency traffic, attach-mode bandwidth. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

diagram

PROMPT
You see cache/memory latency, coherency traffic, attach-mode bandwidth on CXL Attach Modes. Walk through root cause and fix.

STRONG ANSWER
1. Names the layer and transaction identity.
2. Explains CXL.io, CXL.cache, and CXL.mem layer coherent and memory semantics on PCIe infrastructure.
3. Requests CXL mode table, coherency trace, memory window map.
4. Proposes one reduced sequence and one system regression.

WEAK ANSWER
Jumps to widening the interface, increasing FIFO depth, or blaming firmware without evidence.

Diagram to draw on the whiteboard

CXL.io / CXL.cache / CXL.mem

diagram

CXL SUB-PROTOCOLS (share PCIe PHY)

CXL.io   : PCIe-like discovery, config, DMA            (Type 1/2/3)
CXL.cache: device caches host memory coherently        (Type 1/2)
CXL.mem  : host accesses device-attached memory         (Type 2/3)

Type 3 example: memory expander = mostly CXL.mem + CXL.io.

Root-cause tree to narrate

diagram

ROOT-CAUSE TREE — CXL Attach Modes

cache/memory latency, coherency traffic, attach-mode bandwidth looks wrong
        |
   reproducible?
     /        \
   no          yes
   |            |
 flaky env   same first transaction every time?
 / seed         /            \
              yes             no
               |               |
        protocol rule     timing/reset/PVT
        or config bug     or load-dependent

Protocol deep dive

PCIe is reliable packet delivery over unreliable links; debug flows PHY -> DLL -> TLP -> firmware.

Concept diagram

diagram

PCIe DEBUG TOP-DOWN

L0 link healthy?  -> credits OK?  -> TLP completes?  -> driver happy?

Skip a layer and you will mis-own the bug.

Metric graph

diagram

LINK DEGRADE EXAMPLE

target x4 Gen4  ---- ---- ---- ----
actual   x4 Gen4  ---- ---- ---- ----   (eval board)
actual   x1 Gen3  -                   (product board)

Package/SI often shows up as width downgrade, not hard fail.

Metrics and artifacts to collect

link width/speed
replay count
completion timeout
AER error log
LTSSM history

Mini case study

Endpoint enumerated but DMA timed out: completion credits exhausted because a switch port was misconfigured in firmware, not because the endpoint was broken.

Debug branches

If degrade at width/speed, PHY/SI before driver.
If replay storm, link layer before transaction layer.
If CXL coherency bug, separate .io vs .cache vs .mem traffic.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.

Interview whiteboard

Draw layers first, then place the failing transaction on the diagram.

Practice this lesson