Interview Drills for PCIe / CXL Debug focuses on link degrade event count, completion timeout rate, poison/error log. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.
PROMPT
You see link degrade event count, completion timeout rate, poison/error log on PCIe / CXL Debug. Walk through root cause and fix.
STRONG ANSWER
1. Names the layer and transaction identity.
2. Explains debug starts at link health, then checks packet credit, ordering, firmware resource allocation, and endpoint behavior.
3. Requests protocol analyzer capture, AER log, LTSSM history, credit graph.
4. Proposes one reduced sequence and one system regression.
WEAK ANSWER
Jumps to widening the interface, increasing FIFO depth, or blaming firmware without evidence.PCIe/CXL DEBUG ORDER
1. PHY/link : width, speed, LTSSM history, retrain count
2. Link layer: replay/nak rate, credit starvation
3. Txn layer : completion timeouts, ordering, poison/AER
4. Firmware : enumeration, BAR/resource assignment
5. Endpoint : device-specific behavior
Going top-down avoids chasing a software bug that is really a lane bug.ROOT-CAUSE TREE — PCIe / CXL Debug
link degrade event count, completion timeout rate, poison/error log looks wrong
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reproducible?
/ \
no yes
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flaky env same first transaction every time?
/ seed / \
yes no
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protocol rule timing/reset/PVT
or config bug or load-dependentPCIe is reliable packet delivery over unreliable links; debug flows PHY -> DLL -> TLP -> firmware.
PCIe DEBUG TOP-DOWN
L0 link healthy? -> credits OK? -> TLP completes? -> driver happy?
Skip a layer and you will mis-own the bug.LINK DEGRADE EXAMPLE
target x4 Gen4 ---- ---- ---- ----
actual x4 Gen4 ---- ---- ---- ---- (eval board)
actual x1 Gen3 - (product board)
Package/SI often shows up as width downgrade, not hard fail.link width/speed
replay count
completion timeout
AER error log
LTSSM history
Endpoint enumerated but DMA timed out: completion credits exhausted because a switch port was misconfigured in firmware, not because the endpoint was broken.
If degrade at width/speed, PHY/SI before driver.
If replay storm, link layer before transaction layer.
If CXL coherency bug, separate .io vs .cache vs .mem traffic.
Ask: what is the first transaction that deviates, and which spec rule does it test?
Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.
Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.
Draw layers first, then place the failing transaction on the diagram.
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