Enumeration & Link Training: Worked Example

Worked example

Worked Example for Enumeration & Link Training focuses on link width, link speed, LTSSM failure state, enumeration time. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

A product workload shows link width, link speed, LTSSM failure state, enumeration time. The first review mistake is to blame the whole interface. A better review starts by pinning one transaction, proving where protocol progress stopped, and checking whether the observed behavior is legal for Enumeration & Link Training.

Sequence under inspection

SEQUENCE — Enumeration & Link Training

  initiator            interconnect/PHY            target
      |  request (id) ------->  |                     |
      |                         |  forward ----------> |
      |                         |                     | work
      |                         |  <---- response ---- |
      |  <----- complete ------ |                     |
      |
   metric captured here: link width, link speed, LTSSM failure state, enumeration time

LTSSM (link training state machine)

LTSSM (simplified)

  Detect -> Polling -> Configuration -> L0 (active)
                |             |
                v             v
            (fail) <----- Recovery <----- errors/retrain
                                |
                          L0s / L1 (low power)

Degrade symptom: link reaches L0 but at lower width/speed than expected.
Read the LTSSM history, not just the final state.

1. Capture the failing waveform and transaction log.

2. Tag the request ID, address, endpoint, or lane.

3. Find the first response, retry, stall, or missing completion.

4. Compare against LTSSM trace, config space dump, firmware enumeration log.

5. Choose one reversible fix and write the regression list before editing RTL or firmware.

Did the fix work?

BEFORE / AFTER — Enumeration & Link Training

           failing        target
metric  |    ●              ┄┄┄┄┄┄┄
        |     \
        |      \___ ● bounded fix
        |           \
        |            ● validated
        +-------------------------------> change set
Prove the mechanism moved the metric; one good dot is not proof.

Protocol deep dive

PCIe is reliable packet delivery over unreliable links; debug flows PHY -> DLL -> TLP -> firmware.

Concept diagram

PCIe DEBUG TOP-DOWN

L0 link healthy?  -> credits OK?  -> TLP completes?  -> driver happy?

Skip a layer and you will mis-own the bug.

Metric graph

LINK DEGRADE EXAMPLE

target x4 Gen4  ---- ---- ---- ----
actual   x4 Gen4  ---- ---- ---- ----   (eval board)
actual   x1 Gen3  -                   (product board)

Package/SI often shows up as width downgrade, not hard fail.

Metrics and artifacts to collect

• link width/speed

• replay count

• completion timeout

• AER error log

• LTSSM history

Mini case study

Endpoint enumerated but DMA timed out: completion credits exhausted because a switch port was misconfigured in firmware, not because the endpoint was broken.

Debug branches

• If degrade at width/speed, PHY/SI before driver.

• If replay storm, link layer before transaction layer.

• If CXL coherency bug, separate .io vs .cache vs .mem traffic.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.

Narrative walkthrough

A team sees link width, link speed, LTSSM failure state, enumeration time drop 40% after a seemingly small change near Enumeration & Link Training.

They almost widen the interface. Instead they capture id=7 read burst and find W beats never matched AW len.