Mechanism to understand

Mechanism for SPI Modes & Chip-Select Rules focuses on frame error rate, chip-select timing violation, throughput. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

SPI relies on CPOL/CPHA, chip-select timing, shift order, and device-specific framing agreements. Think of it as a contract enforced at boundaries: the sender promises stability and legality, the receiver promises forward progress, and the fabric in between promises not to silently change identity or ordering.

• Identify the transaction boundary: request, data, response, completion, or retry.

• Identify the flow-control boundary: valid/ready, grant, credit, FIFO depth, or lane state.

• Identify what the receiver is allowed to assume and what the sender must hold stable.

Layered view

PROTOCOL STACK VIEW — SPI Modes & Chip-Select Rules

software / firmware intent
        |
        v
transaction semantics: address, ID, length, attributes, ordering
        |
        v
link / channel behavior: handshake, credits, backpressure, retries
        |
        v
physical or timing layer: clocking, reset, pins, lanes, PHY
        |
        v
observability: waveform, VIP transaction, counter, analyzer trace

Debug rule: never jump layers without carrying the transaction identity with you.

SPI modes (CPOL/CPHA)

SPI MODES

Mode | CPOL | CPHA | sample edge
-----+------+------+-------------
  0  |  0   |  0   | rising
  1  |  0   |  1   | falling
  2  |  1   |  0   | falling
  3  |  1   |  1   | rising

WAVE (Mode 0):
CS   ‾‾\____________________/‾‾
SCLK ____|‾|_|‾|_|‾|_|‾|________
MOSI    D7  D6  D5  D4
        ^ sampled on rising edge

Layer responsibilities

LAYER RESPONSIBILITY — SPI Modes & Chip-Select Rules

layer          owns                         common failure
-----------    --------------------------   -----------------------
software       intent, ordering needs       wrong assumption
transaction    id/addr/len/attributes       ordering / outstanding
link/channel   handshake, credits, retry    backpressure / deadlock
physical       clock/reset/lanes/PHY        timing / training / SI
observability  waveform/log/counter         missing evidence

Protocol deep dive

I2C/SPI/UART bugs are contract bugs: timing, reset value, IRQ type, and DMA watermark.

Concept diagram

PERIPHERAL CONTRACT

firmware writes regs -> RTL state machine -> pins -> board -> device
        ^                    |
        +------- IRQ/DMA ----+

If IRQ is level but driver assumes edge, you get lost events.

Metric graph

FIFO WATERMARK vs DMA

FIFO fill
 100%|        *** overrun risk
  75%|     ***
  50%|  ***     <- ideal DMA trigger band
  25%| *
   0%+----------------> time

Metrics and artifacts to collect

• NACK rate

• overrun count

• CS setup/hold violations

• IRQ miss rate

Mini case study

SPI flash worked in loopback but failed in system: CS deasserted one cycle early relative to device hold time. Board + RTL + mode bits together formed the contract.

Debug branches

• If overrun, FIFO depth vs ISR latency vs DMA burst.

• If NACK on I2C, pull-ups, speed, and clock stretch.

• If garbage data, CPOL/CPHA and MSB/LSB first.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.

Mechanism deep dive

SPI relies on CPOL/CPHA, chip-select timing, shift order, and device-specific framing agreements.

Walk the transaction forward: request accepted → data moves → response completes → software visible effect.