I2C Timing & Arbitration: Software / Programmer View

Software and programmer view

Register reset values, IRQ polarity/edge, and polling vs interrupt drive driver correctness.

What programmers feel

• Timeouts with healthy-looking hardware counters

• Data corruption without obvious ECC/CRC

• Ordering surprises under multi-threaded drivers

• Performance cliffs when payload size changes

API / driver implications

• Descriptor alignment and cache line sharing

• Fence/barrier placement around DMA

• IRQ type (level vs edge) and clear sequence

• Memory-mapped register access ordering

Compiler and runtime interaction

• Volatile and barrier semantics for device memory

• Struct padding affecting burst efficiency

• Batching policy in userspace drivers

Software-side mitigations

• Pad structures to cache lines

• Pin buffers and use coherent DMA where required

• Expose hardware counters to software profilers

• Document legal outstanding depth and ordering

SOFTWARE EXAMPLE — I2C Timing & Arbitration

// Bad: assumes ordering across unrelated IDs without fence
dma_start(ch0); dma_start(ch1); cpu_read(result); // may see stale

// Better: document which completions are ordered and insert barrier
dma_start(ch0); wait_completion(ch0); cpu_read(result);

Layer the driver touches

LAYER RESPONSIBILITY — I2C Timing & Arbitration

layer          owns                         common failure
-----------    --------------------------   -----------------------
software       intent, ordering needs       wrong assumption
transaction    id/addr/len/attributes       ordering / outstanding
link/channel   handshake, credits, retry    backpressure / deadlock
physical       clock/reset/lanes/PHY        timing / training / SI
observability  waveform/log/counter         missing evidence

Protocol deep dive

I2C/SPI/UART bugs are contract bugs: timing, reset value, IRQ type, and DMA watermark.

Concept diagram

PERIPHERAL CONTRACT

firmware writes regs -> RTL state machine -> pins -> board -> device
        ^                    |
        +------- IRQ/DMA ----+

If IRQ is level but driver assumes edge, you get lost events.

Metric graph

FIFO WATERMARK vs DMA

FIFO fill
 100%|        *** overrun risk
  75%|     ***
  50%|  ***     <- ideal DMA trigger band
  25%| *
   0%+----------------> time

Metrics and artifacts to collect

• NACK rate

• overrun count

• CS setup/hold violations

• IRQ miss rate

Mini case study

SPI flash worked in loopback but failed in system: CS deasserted one cycle early relative to device hold time. Board + RTL + mode bits together formed the contract.

Debug branches

• If overrun, FIFO depth vs ISR latency vs DMA burst.

• If NACK on I2C, pull-ups, speed, and clock stretch.

• If garbage data, CPOL/CPHA and MSB/LSB first.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.

Principal review addendum

Re-read I2C Timing & Arbitration against one concrete product workload, not a synthetic directed test.

I2C shares open-drain wires with address arbitration, acknowledge cycles, and optional clock stretching.