Interface Protocols · All levels

I2C Timing & Arbitration: Interview Drills

Interview Drills for I2C Timing & Arbitration.

Interview drills

Interview Drills for I2C Timing & Arbitration focuses on NACK rate, clock-stretch duration, bus recovery time. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

diagram

PROMPT
You see NACK rate, clock-stretch duration, bus recovery time on I2C Timing & Arbitration. Walk through root cause and fix.

STRONG ANSWER
1. Names the layer and transaction identity.
2. Explains I2C shares open-drain wires with address arbitration, acknowledge cycles, and optional clock stretching.
3. Requests SCL/SDA waveform, transaction log, pull-up timing check.
4. Proposes one reduced sequence and one system regression.

WEAK ANSWER
Jumps to widening the interface, increasing FIFO depth, or blaming firmware without evidence.

Diagram to draw on the whiteboard

I2C start/stop and ACK waveform

diagram

I2C FRAME

SDA  ‾‾\__/‾‾\__ ... __/‾‾  ‾‾\__/‾‾
SCL  ‾‾‾‾\_/‾\_/‾ ... \_/‾‾‾‾‾‾‾‾
      S  A6..A0 R/W ACK  data..  ACK  P
      ^                            ^
    START                        STOP

START: SDA falls while SCL high
STOP : SDA rises while SCL high
ACK  : receiver pulls SDA low on the 9th clock

Root-cause tree to narrate

diagram

ROOT-CAUSE TREE — I2C Timing & Arbitration

NACK rate, clock-stretch duration, bus recovery time looks wrong
        |
   reproducible?
     /        \
   no          yes
   |            |
 flaky env   same first transaction every time?
 / seed         /            \
              yes             no
               |               |
        protocol rule     timing/reset/PVT
        or config bug     or load-dependent

Protocol deep dive

I2C/SPI/UART bugs are contract bugs: timing, reset value, IRQ type, and DMA watermark.

Concept diagram

diagram

PERIPHERAL CONTRACT

firmware writes regs -> RTL state machine -> pins -> board -> device
        ^                    |
        +------- IRQ/DMA ----+

If IRQ is level but driver assumes edge, you get lost events.

Metric graph

diagram

FIFO WATERMARK vs DMA

FIFO fill
 100%|        *** overrun risk
  75%|     ***
  50%|  ***     <- ideal DMA trigger band
  25%| *
   0%+----------------> time

Metrics and artifacts to collect

NACK rate
overrun count
CS setup/hold violations
IRQ miss rate

Mini case study

SPI flash worked in loopback but failed in system: CS deasserted one cycle early relative to device hold time. Board + RTL + mode bits together formed the contract.

Debug branches

If overrun, FIFO depth vs ISR latency vs DMA burst.
If NACK on I2C, pull-ups, speed, and clock stretch.
If garbage data, CPOL/CPHA and MSB/LSB first.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

Connect every protocol claim to a transaction identity and measurable metric.
Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

Debugging timeouts without finding the first bad transaction.
Quoting peak bus width without payload efficiency and retry overhead.
Treating VIP compliance as a substitute for system integration replay.

Interview whiteboard

Draw layers first, then place the failing transaction on the diagram.

Practice this lesson