PROMPT
You see NACK rate, clock-stretch duration, bus recovery time on I2C Timing & Arbitration. Walk through root cause and fix.

STRONG ANSWER
1. Names the layer and transaction identity.
2. Explains I2C shares open-drain wires with address arbitration, acknowledge cycles, and optional clock stretching.
3. Requests SCL/SDA waveform, transaction log, pull-up timing check.
4. Proposes one reduced sequence and one system regression.

WEAK ANSWER
Jumps to widening the interface, increasing FIFO depth, or blaming firmware without evidence.

I2C FRAME

SDA  ‾‾\__/‾‾\__ ... __/‾‾  ‾‾\__/‾‾
SCL  ‾‾‾‾\_/‾\_/‾ ... \_/‾‾‾‾‾‾‾‾
      S  A6..A0 R/W ACK  data..  ACK  P
      ^                            ^
    START                        STOP

START: SDA falls while SCL high
STOP : SDA rises while SCL high
ACK  : receiver pulls SDA low on the 9th clock

ROOT-CAUSE TREE — I2C Timing & Arbitration

NACK rate, clock-stretch duration, bus recovery time looks wrong
        |
   reproducible?
     /        \
   no          yes
   |            |
 flaky env   same first transaction every time?
 / seed         /            \
              yes             no
               |               |
        protocol rule     timing/reset/PVT
        or config bug     or load-dependent

PERIPHERAL CONTRACT

firmware writes regs -> RTL state machine -> pins -> board -> device
        ^                    |
        +------- IRQ/DMA ----+

If IRQ is level but driver assumes edge, you get lost events.

FIFO WATERMARK vs DMA

FIFO fill
 100%|        *** overrun risk
  75%|     ***
  50%|  ***     <- ideal DMA trigger band
  25%| *
   0%+----------------> time