I2C Timing & Arbitration: Step-by-Step Walkthrough

Step-by-step analysis walkthrough

Follow this when you own I2C Timing & Arbitration in a protocol review or bring-up war room.

1. State expected transaction in plain language (who initiates, what completes).

2. Draw layer stack and mark clock/reset boundaries.

3. List channels: request, data, response, snoop, credit, or lane.

4. Tag ID/address/endpoint on the failing run.

5. Find first cycle where progress stops or semantics change.

6. Check bridge: width, ID remap, burst, ordering attributes.

7. Check flow control: ready, credit, FIFO, link state.

8. Check firmware/register mode vs hardware capability.

9. Build minimal replay; confirm legal vs illegal per spec.

10. Estimate metric delta from proposed fix.

11. Run compliance + product traffic regression matrix.

12. Write signoff memo with owners and artifacts attached.

Artifacts to collect

• SCL/SDA waveform, transaction log, pull-up timing check

• VIP transaction log

• Waveform with annotations

• Spec clause reference

• Regression manifest

Decision memo template

PROTOCOL DECISION MEMO — I2C Timing & Arbitration
metric:
transaction id:
layer:
hypothesis:
experiment:
fix:
validation:
owners: peripheral owner, board owner, driver owner

Reference visuals

I2C start/stop and ACK waveform

I2C FRAME

SDA  ‾‾\__/‾‾\__ ... __/‾‾  ‾‾\__/‾‾
SCL  ‾‾‾‾\_/‾\_/‾ ... \_/‾‾‾‾‾‾‾‾
      S  A6..A0 R/W ACK  data..  ACK  P
      ^                            ^
    START                        STOP

START: SDA falls while SCL high
STOP : SDA rises while SCL high
ACK  : receiver pulls SDA low on the 9th clock

Protocol deep dive

I2C/SPI/UART bugs are contract bugs: timing, reset value, IRQ type, and DMA watermark.

Concept diagram

PERIPHERAL CONTRACT

firmware writes regs -> RTL state machine -> pins -> board -> device
        ^                    |
        +------- IRQ/DMA ----+

If IRQ is level but driver assumes edge, you get lost events.

Metric graph

FIFO WATERMARK vs DMA

FIFO fill
 100%|        *** overrun risk
  75%|     ***
  50%|  ***     <- ideal DMA trigger band
  25%| *
   0%+----------------> time

Metrics and artifacts to collect

• NACK rate

• overrun count

• CS setup/hold violations

• IRQ miss rate

Mini case study

SPI flash worked in loopback but failed in system: CS deasserted one cycle early relative to device hold time. Board + RTL + mode bits together formed the contract.

Debug branches

• If overrun, FIFO depth vs ISR latency vs DMA burst.

• If NACK on I2C, pull-ups, speed, and clock stretch.

• If garbage data, CPOL/CPHA and MSB/LSB first.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

• Connect every protocol claim to a transaction identity and measurable metric.

• Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

• Debugging timeouts without finding the first bad transaction.

• Quoting peak bus width without payload efficiency and retry overhead.

• Treating VIP compliance as a substitute for system integration replay.

Principal review addendum

Re-read I2C Timing & Arbitration against one concrete product workload, not a synthetic directed test.

I2C shares open-drain wires with address arbitration, acknowledge cycles, and optional clock stretching.