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Peripheral Integration Debug: Interview Drills

Interview Drills for Peripheral Integration Debug.

Interview drills

Interview Drills for Peripheral Integration Debug focuses on driver timeout, interrupt miss rate, DMA underrun/overrun. The goal is to connect the observable symptom to protocol mechanism, ownership, and regression risk.

diagram
PROMPT
You see driver timeout, interrupt miss rate, DMA underrun/overrun on Peripheral Integration Debug. Walk through root cause and fix.

STRONG ANSWER
1. Names the layer and transaction identity.
2. Explains low-speed bugs are usually contract bugs between register map, reset state, interrupt policy, DMA, and firmware polling.
3. Requests register dump, interrupt trace, DMA descriptor log, reset sequence.
4. Proposes one reduced sequence and one system regression.

WEAK ANSWER
Jumps to widening the interface, increasing FIFO depth, or blaming firmware without evidence.

Diagram to draw on the whiteboard

Peripheral contract surface

diagram
PERIPHERAL = REGISTER + IRQ + DMA CONTRACT

  CPU --MMIO--> [ registers ]   (control/status)
       <--IRQ--  [ event   ]    (level vs edge!)
  DMA <--data--> [ FIFO    ]    (watermarks)

Most bugs: reset value wrong, IRQ type mismatch, FIFO watermark vs DMA burst.

Root-cause tree to narrate

diagram
ROOT-CAUSE TREE — Peripheral Integration Debug

driver timeout, interrupt miss rate, DMA underrun/overrun looks wrong
        |
   reproducible?
     /        \
   no          yes
   |            |
 flaky env   same first transaction every time?
 / seed         /            \
              yes             no
               |               |
        protocol rule     timing/reset/PVT
        or config bug     or load-dependent

Protocol deep dive

I2C/SPI/UART bugs are contract bugs: timing, reset value, IRQ type, and DMA watermark.

Concept diagram

diagram
PERIPHERAL CONTRACT

firmware writes regs -> RTL state machine -> pins -> board -> device
        ^                    |
        +------- IRQ/DMA ----+

If IRQ is level but driver assumes edge, you get lost events.

Metric graph

diagram
FIFO WATERMARK vs DMA

FIFO fill
 100%|        *** overrun risk
  75%|     ***
  50%|  ***     <- ideal DMA trigger band
  25%| *
   0%+----------------> time

Metrics and artifacts to collect

  • NACK rate

  • overrun count

  • CS setup/hold violations

  • IRQ miss rate

Mini case study

SPI flash worked in loopback but failed in system: CS deasserted one cycle early relative to device hold time. Board + RTL + mode bits together formed the contract.

Debug branches

  • If overrun, FIFO depth vs ISR latency vs DMA burst.

  • If NACK on I2C, pull-ups, speed, and clock stretch.

  • If garbage data, CPOL/CPHA and MSB/LSB first.

Senior review question

Ask: what is the first transaction that deviates, and which spec rule does it test?

Key takeaways

  • Connect every protocol claim to a transaction identity and measurable metric.

  • Store the artifact (waveform, log, counter) next to every signoff decision.

Common pitfalls

  • Debugging timeouts without finding the first bad transaction.

  • Quoting peak bus width without payload efficiency and retry overhead.

  • Treating VIP compliance as a substitute for system integration replay.

Interview whiteboard

Draw layers first, then place the failing transaction on the diagram.

Practice this lesson