Software sees power as three states and a wake latency; the integrator sees everything underneath: which blocks share a switch, which signals need clamping, what order the rails, clocks and resets come up in, and what happens when any of it is wrong by one cycle. NanoSoC keeps the physics small — two power domains, one 0.9 V supply, 114 isolation clamps, a 14.073 µs wake and a single always-on controller — but it contains every classic power-integration problem: a switchable domain that must be isolated before it is reset and powered off, a sequencer that must handshake with the reset controller, a cold start where the crystal, the PLL and three resets line up in one 53.948 µs timeline, a board supply that can brown out under load, an 82.74 mW RUN budget that becomes heat, and a voltage-frequency ordering rule that must never be inverted. This section teaches power as the integrator owns it: domains and states first, then the circuitry that makes them safe, then the sequences, the supply, the heat, and the operating points. Every number about NanoSoC is a NanoSoC teaching value used consistently across the course; any other number is labelled illustrative.
Topic | What it covers | After it you can... |
|---|---|---|
PD_AON and PD_SW, the RUN, IDLE and SLEEP table, what is retained | Place every NanoSoC block in its domain and cost each power state in milliwatts. | |
Where the 114 clamps go, enable timing, save and restore, the UPF view | Check every crossing from PD_SW into PD_AON and review an isolation sequence. | |
The sequencer state machine, handshakes with the reset controller, timeouts | Read the NanoSoC power sequence as an FSM and size its timeouts. | |
Supply ramp, POR, crystal, PLL lock, reset release and boot as one timeline | Recompute the 53.948 µs hardware timeline and say where boot time really goes. | |
Rail order, power-good, PMIC handshake, brown-out, the package and board view | Specify a rail order with power-good checks and a brown-out response. | |
From milliwatts to degrees, throttling policy, sensors | Turn the NanoSoC power table into a temperature and a throttling plan. | |
Voltage and frequency ordering, clock switching, safe operating points | Review a voltage-frequency transition for ordering, crossing and regulator risk. |
Suggested order: top to bottom. Domains and states define what must be built; isolation and the sequencer build it; cold start strings every wait into one timeline; supply sequencing zooms out to the board; thermal and DVFS close the loop on what the chip may do once it is running. Readers chasing a wake failure can start at the sequencer topic and follow the links back to isolation; readers sizing a product start at thermal. For the low-power vocabulary and mechanism behind these lessons see Power Domain Basics; for the reset side of every sequence see Reset Is a System Contract.
Because DVFS and thermal manage a running chip, while domains, isolation, sequencing and supply decide whether the chip wakes at all. The operating points only make sense once the rails and the wake sequence are correct.