When NanoSoC sleeps, the PLL is off, both fast clocks are dead, and one 24 MHz crystal clock keeps eight blocks alive: the reset and power controller, the PLL, the interrupt controller, the UART, SPI, GPIO, SRAM0 and the ROM. This topic places those blocks, writes the wake policy for the sources that really exist, and then does something different in two lessons: it treats a watchdog and a wake timer as a clearly labelled extension. NanoSoC has no watchdog, no real-time clock and no timers: there is no such block in its list of sixteen, no RST_CAUSE bit for them (the four causes are POR, PAD, SW and WAKE) and no interrupt input (inputs 6 and 7 are reserved and tied to zero). The extension lessons show what adding one would change in the reset tree, the cause register and the interrupt map, which is the integrator's real work. For the block circuits see Counters and Timers and Watchdog Timer Example.
Lesson | After it you can... |
|---|---|
Place every always-on block on its clock and power domain, and place a wake timer if you add one (extension). | |
List what a watchdog would change in the reset tree, RST_CAUSE and the interrupt map (extension, not in NanoSoC). | |
Write the wake policy for NanoSoC's real sources: what resets, what interrupts, and what wakes from sleep. |
Suggested order: top to bottom. Placement first, because both the wake policy and the extension assume the always-on domain; then the extension, which shows how a new block changes three shared tables; then the policy, which closes the topic. Every number inside the two extension passages is an illustrative teaching value, labelled as such; every number about the existing chip comes from the NanoSoC specification.
It must fire when software hangs, including hangs that stop the PLL or gate the fast clocks. On clk_sys it dies with the logic it is meant to supervise; on the always-on crystal clock it outlives every failure it guards except a supply loss.