NanoSoC has one clock source and three clocks. This topic derives all three from the source: what the 24 MHz crystal guarantees, how the PLL multiplies it to 768 MHz, how two dividers produce 192 and 96 MHz, why the slow clock bypasses the PLL entirely, and how long the chip waits for lock. Every number comes from the NanoSoC specification.
Lesson | After it you can... |
|---|---|
Derive every NanoSoC frequency from 24 MHz and check the VCO range. | |
Integrate the PLL macro and say what holds the chip until lock. | |
Recompute the NanoSoC PLL settings from scratch and reject bad ones. |
Suggested order: top to bottom. Frequencies first, then the wrapper that owns them, then the calculator that proves the settings. The divider detail continues in Dividers, Muxes and Glitch-Free Switching.
The 24 MHz crystal clock keeps running with everything on it: peripherals, reset controller and wake logic. The 192 and 96 MHz clocks derived from the PLL stop or go out of spec, so the CPU and fabric stop with them.