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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
    • Clock Sources and PLLs
    • Dividers, Muxes and Glitch-Free Switching
    • Clock Gating Architecture
    • Clock Domain Planning
    • Top-Level Crossings
      • The Ten Crossings
      • Choosing a Mechanism per Crossing
      • Crossing Review Checklist
    • Always-On Domain, Wake Policy and a Timer Extension
    • Reset Sources and Reset Tree
    • Reset Sequencing and Release
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC14
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←Clock and Reset Architecture
  1. Topics
  2. SoC Design
  3. Clock and Reset Architecture
  4. Top-Level Crossings

Part 5 of 14Part 5 of 14/Clock and Reset ArchitectureAll levels

Top-Level Crossings

The ten NanoSoC crossings: what crosses where, which mechanism carries each, and the review checklist.

  • 3topics
  • 3lessons

Ten groups of signals cross NanoSoC's domains, and each has exactly one safe mechanism: FIFOs for the AXI channels, a request-and-acknowledge handshake for the APB bridge, two-flop synchronisers for every single bit. This topic inventories all ten, teaches how to choose the mechanism for a new crossing, and ends with the checklist the review signs. The circuits themselves belong to the CDC & RDC course; this topic decides where they sit and why. For the protocols see Async FIFO CDC and Handshake Protocols Across Domains; for choosing synchronisers see Synchronizer Selection Guide.

Lesson

After it you can...

The Ten Crossings

Recite all ten crossings with signals and mechanisms.

Choosing a Mechanism per Crossing

Assign FIFO, handshake or two flops to any new crossing and price it.

Crossing Review Checklist

Run the top-level crossing review and know what evidence closes it.

Suggested order: top to bottom. Inventory first, because mechanism choice needs the full signal list; then the decision rules with their arithmetic; then the checklist, which assumes both. Readers who design crossing circuits should read the linked CDC lessons alongside the second lesson.

Check yourself State the course rule for crossings in one sentence.

Nothing multi-bit crosses without a handshake or a FIFO, and nothing single-bit crosses without two flops. Clock-gating cells are not crossings.

Expect to whiteboard the ten crossings grouped by mechanism: one FIFO pair (X1, X2), one handshake pair (X3, X4), five level-sync groups (X5, X6, X7, X8, X10) and one external-input group (X9): 2 + 2 + 5 + 1 = 10. Grouping beats reciting.

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See also

  • Clock Sources and PLLs
  • Dividers, Muxes and Glitch-Free Switching
  • Clock Gating Architecture