Three clocks is a decision, not a coincidence: each domain costs crossings, synchronisers and verification, and each missing domain costs power or performance. This topic plans the NanoSoC domains from scratch, prices the ratios, explains why two clocks from one PLL still sign off as asynchronous, and ends with the table that assigns every block exactly one domain. For finding domains in general see Identifying Domains; for placing boundaries to cut crossings see CDC-Aware Partitioning.
Lesson | After it you can... |
|---|---|
Justify three domains and quote the 8:4:1 ratios with periods. | |
Say why one PLL does not make two clocks synchronous for signoff. | |
Assign every NanoSoC block to its domain and check the assignment. |
Suggested order: top to bottom. Choose the domains, then decide how each pair signs off, then write the table that records both. The crossing inventory in the next topic consumes this table directly.
Which crossings does it add and remove, and does the DMA's traffic justify its own clock? On NanoSoC the DMA shares clk_sys with its memories and bus, so a fourth domain buys little and adds crossings on every stream and register path.