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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC14
    • Capstone Brief
    • Stage 1: Memory Map and Interconnect
    • Stage 2: Clocks, Resets, Power
    • Stage 3: Interrupts and Boot
    • Stage 4: Verification and Signoff
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←SoC Design
  1. Topics
  2. SoC Design
  3. Capstone: Integrate NanoSoC

Part 14 of 14Part 14 of 14/Capstone: Integrate NanoSoCAll levels

Capstone: Integrate NanoSoC

Play the integrator for NanoSoC: five stages, each producing an artefact checked by a runnable engine, ending in a signoff manifest check.

  • 5topics
  • 14lessons

You are the integrator for NanoSoC v1: one 32-bit core, a 2-master by 4-slave AXI4 fabric at 96 MHz, 64 KB plus 64 KB of SRAM, a 16 KB boot ROM, the streaming DMA behind its stream bridge, and five slow peripherals behind an APB bridge. Each stage of this lab produces one artefact, a map table, a clock and reset plan, an interrupt and boot record, a test matrix, and each artefact is checked by the same small runnable engine that is embedded in every lesson. Every check is a function of the design data and is shown to fail when its bug is injected. The lab ends with a signoff manifest check that reads every stage artefact and prints PASS only when every stage agrees, and a readiness review that lists what is still open, including a known hole in the security partition.

Topic

What it covers

After it you can...

Capstone Brief

Requirements, deliverables, working data, rubric, the ten planted bugs

State what NanoSoC v1 must do and how the lab is graded.

Stage 1: Memory Map and Interconnect

Map table, overlap and alignment checks, decode, response codes, link sizing

Prove the map has no overlap and name the bottleneck link.

Stage 2: Clocks, Resets, Power

Clock plan, ten crossings, reset tree and order, domains, isolation, power-up

Release resets in an order no boot can outrun.

Stage 3: Interrupts and Boot

Interrupt map and latency, DMA sequence, boot flow, secure partition

Programme a DMA job that cannot confuse its lengths or its keys.

Stage 4: Verification and Signoff

Test matrix for all ten bugs, manifest, waiver ageing, final check

Run one script that prints PASS only when everything agrees.

Suggested order: top to bottom, about 12 hours with the worked checks (NanoSoC teaching value: the Capstone Brief 1 hour, each stage 2 to 3 hours, signoff review 1 hour). The map comes first because every later stage quotes addresses; clocks, resets and power come as one stage because release order ties them together; interrupts and boot follow because the boot code programmes them; verification closes the lab because its matrix points back at every stage. Each lesson runs standalone: goal, inputs, steps, the checker to run, expected output, what each failure means, a hint ladder, and an interview follow-up.

Check yourself Why does the manifest check print PASS only when every stage agrees, rather than one PASS per stage?

Per-stage checks pass against their own inputs, so a map fix that never reached the boot code would still show four green stages. The manifest cross-checks the artefacts against each other, which is the only check that catches drift between stages.

Expect to walk this lab on a whiteboard: one map row, one link number, one crossing, one release-order rule, one interrupt path, one boot share, one manifest condition. Each stage of the lab is one column of that board.

Related topics

  • Up: SoC Design course hub

  • NanoSoC Tour

  • Glossary

  • PD Capstone: Block Implementation Lab

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See also

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path