Stage 2: Clocks, Resets, Power · soc

Part 14 of 14Capstone: Integrate NanoSoCAll levels

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Stage 2 produces the time plan of the chip: the PLL chain that makes 192, 96 and 24 MHz, the ten crossings with their mechanisms, the reset tree that releases the CPU last, the two power domains with 114 isolation clamps, and the 14.073 us wake timeline. Planted bugs 2, 5, 6 and 10 live here: a release order, a missing synchroniser, two missing clamps, and a clock gate with no bridge watchdog.

Lesson	After it you can...
Clock Plan and Crossing Inventory	Derive every clock and prove each crossing has a mechanism.
Reset Tree and Release Order	Sequence the release so no fetch outruns the fabric.
Power Domains, Isolation and Power-Up	Count the clamps and walk the power-up timeline.

Suggested order: top to bottom. Clocks first, because crossings name the domains; resets second, because release waits on lock; power last, because its sequence reuses both. The rule for the whole stage: nothing multi-bit crosses without a handshake or a FIFO, and nothing single-bit crosses without two flops.

Check yourself clk_cpu and clk_sys come from one PLL. Why does signoff still treat them as asynchronous?

Different divider roots and separate trees mean no bounded phase relation at the sinks, so the only safe contract is the asynchronous one with FIFOs.

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