This topic is the contract for the whole lab: what NanoSoC v1 must do, what you hand in at each stage, which numbers you may quote, and how the work is graded. Ten integration bugs are injected into the clean lab data, one at a time. Stages 1 to 3 each catch their own with a checker that must fail on the bug, and stage 4 proves all ten.
Lesson | After it you can... |
|---|---|
Quote the v1 requirement set and name each stage's artefact. | |
State all ten planted bugs and how the rubric scores them. |
Suggested order: requirements first, then the bug list, because the bug table only makes sense once the correct behaviour is stated. Keep this topic open beside every later stage: any number you quote that is not here or in the lesson tables is wrong until proven.
The DMA runs at clk_sys, 96 MHz; 100 MHz is the UVM bench's testbench choice, not a NanoSoC value.