Nobody designs a chip alone, and nobody integrates one by accident. A block owner proves their block works; the architect chooses the structure; the integrator makes the 16 blocks (15 modules plus the PLL macro) of NanoSoC behave as one chip, from the first memory map to the last waiver. That job is mostly ownership, not cleverness: knowing which handoff is incomplete, which contract changed without a version bump, which requirement never became a budget, and catching each at the stage where the fix costs an afternoon rather than a respin. This section opens the course with that desk view. It teaches no protocol mechanics and no timing analysis; those live in their owner courses. It teaches what the integrator owns, the milestones a chip passes from specification to tapeout, the contracts that hold blocks together, and how to read a specification as a list of constraints and budgets. Every lesson is worked on NanoSoC, the chip this course builds together.
Topic | What it covers | After it you can... |
|---|---|---|
What the integrator owns versus block owners, architects, verification, PD and software; what a handoff must contain; the NanoSoC cast | Route any integration symptom to its owner and reject an incomplete handoff. | |
Milestones and deliverables from specification to tapeout, what is frozen when, where bugs are cheapest to catch | Name every milestone gate, say what is frozen at each, and price a late bug. | |
Interfaces as contracts across six facets, who owns each contract, RACI, change control, the hardware-software contract and errata | Write a contract for an interface, assign its owners, and run the errata process. | |
Turning requirements into constraints and budgets, hunting ambiguity, a worked requirement-to-budget trace for NanoSoC | Convert a specification paragraph into checked budgets for power, area, bandwidth and boot time. |
Suggested order: top to bottom. The role comes first, because every later lesson assumes you know who owns what; then the flow, because contracts and budgets only make sense against milestones; then contracts, because the specification lesson spends them. Readers preparing for an interview can read the first topic and the errata lesson, then jump to the worked trace. For the implementation steps inside physical design see PD Flow Overview; for the synthesis box in the flow see Synthesis Flow Overview.
It is an integration ownership bug: no single source owned both consumers. The fix is one machine-readable map generating the RTL, the header and the documentation, plus a model-versus-RTL check at every handoff.