SoC Architecture Tradeoffs

Section goal

Train architects to make PPA decisions that remain executable through PD, power signoff, timing closure, and verification.

Mechanism to narrate

• Most schedule slips start as architecture assumptions that never got physically validated.

• Tradeoff quality is measured by closure confidence, not only simulated performance gain.

• A strong architecture owner names budgets, owners, evidence, and rollback criteria.

Senior course bar for this section

• Every topic should end with an architecture decision, not only concept recall.

• Every fix should state expected metric movement and likely regression surface.

• Every open assumption should have an owner, tag, and review date.

• Every recurring issue should become a methodology guardrail or checklist item.

1. ppa-at-system-level/ — PPA at System Level

2. floorplan-aware-architecture/ — Floorplan-Aware Architecture

3. chip-budget-negotiation/ — Chip Budget Negotiation

4. architecture-signoff/ — Architecture Signoff

Related topics

• Floorplanning

• Power Signoff

• Timing Closure

• Physical Integration

Key takeaways

• Architecture decisions must be reviewable by PD, STA, power, and verification leads.

• Late closure pain usually reflects early budget ambiguity, not just tool limitations.

Section deep dive

Chip architecture signoff is a negotiated PPA contract across teams.

Concept diagram

PPA NEGOTIATION MAP

Architecture target
   │
   ├─ Performance: IPC, latency, bandwidth, QoS
   ├─ Power: dynamic, leakage, thermal envelope
   ├─ Area: SRAM, logic, NoC links, floorplan
   ├─ Verification: state space, tests, formal complexity
   └─ PD: timing, placement, macro distance, routing channels

A staff architect makes the trade visible before it becomes a crisis.

Metric graph

PPA OPTION CHART

Option          Perf      Power     Area      Risk
A wider core    +++       ---       --        high
B better cache  ++        -         --        med
C SW locality   +         +         0         med
D NoC QoS       +         -         -         low

Pick based on product objective, not elegance.

Metrics and artifacts

• PPA dashboard

• floorplan distance budget

• NoC BW matrix

• verification closure status

Mini case study

CPU–memory macro distance violated latency budget — architecture accepted lower CPU frequency rather than respin floorplan one week before tapeout.

Debug branches

• If PD pushes back, bring numeric latency/power models not opinions.

• If signoff yellow, document owner, mitigation, and decision date.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

• Connect every architecture claim to a workload and measurable metric.

• State verification and PPA impact before proposing design changes.

Common pitfalls

• Feature-driven design without MPKI/IPC/bandwidth evidence.

• Ignoring coherency and NoC traffic in cache and accelerator sizing.