DenseChip

Computer Architecture · All levels

NoC and Interconnect Architecture

Design and debug scalable on-chip networks that survive bandwidth growth, latency constraints, and mixed traffic quality-of-service requirements.

Section goal

Turn interconnect from a hidden bottleneck into a measurable, verifiable, and evolvable subsystem.

Mechanism to narrate

  • Topology choices define latency floor and wiring pressure long before RTL is frozen.

  • Routing and flow control policies are correctness and performance contracts, not tuning knobs.

  • QoS decisions must be backed by observability hooks or they fail silently in silicon.

Senior course bar for this section

  • Every topic should end with an architecture decision, not only concept recall.

  • Every fix should state expected metric movement and likely regression surface.

  • Every open assumption should have an owner, tag, and review date.

  • Every recurring issue should become a methodology guardrail or checklist item.

  1. noc-topology/ — NoC Topology Tradeoffs

  2. routing-flow-control/ — Routing and Flow Control

  3. qos-and-arbitration/ — QoS and Arbitration Policies

  4. noc-debug/ — NoC Debug and Observability

Related topics

Key takeaways

  • A scalable NoC architecture is equal parts topology, protocol discipline, and debug visibility.

Section deep dive

NoC is a queueing system — bandwidth, latency, and deadlock are coupled.

Concept diagram

diagram
NoC TOPOLOGY SKETCH

CPU0 ──┐      ┌── LLC0 ── DRAM0
       R0 ─── R1
CPU1 ──┘      │
              R2 ─── R3 ── GPU/DMA
              │      │
             NPU    LLC1 ── DRAM1

Look for: hot links, cyclic dependencies, VC starvation, and tail latency.

Metric graph

diagram
LATENCY DISTRIBUTION

p50    ██████  32 ns
p90    ████████████  71 ns
p99    ████████████████████████  210 ns
p99.9  █████████████████████████████████  480 ns

Averages hide QoS failures.

Metrics and artifacts

  • link utilization

  • average latency by master

  • retry/backpressure counts

  • QoS violation log

Mini case study

Average latency looks fine but tail latency spikes for CPU coherent reads when GPU DMA runs. QoS and separate VCs fix the starvation without doubling link width.

Debug branches

  • If deadlock, check credit loops and routing restrictions first.

  • If latency tail long, inspect arbitration and buffer depth.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

  • Connect every architecture claim to a workload and measurable metric.

  • State verification and PPA impact before proposing design changes.

Common pitfalls

  • Feature-driven design without MPKI/IPC/bandwidth evidence.

  • Ignoring coherency and NoC traffic in cache and accelerator sizing.

Practice this lesson