On-chip networks carry every cache refill, DMA burst and IO transfer. Topology sets the hop count, routing keeps packets moving without deadlock, credits keep buffers safe, arbitration decides who waits, and triage finds the bottleneck when tails explode.
Family (64 nodes) | Diameter | Bisection per direction | Cost note |
|---|---|---|---|
Mesh 8x8 | 14 hops | 8 links | Short local wires, predictable layout |
Torus 8x8 | 8 hops | 16 links | Long wrap wires around the die edge |
Ring of 64 | 32 hops | 2 links | Simplest layout, thinnest cut |
Crossbar 64x64 | 1 hop | 32 links | 4096 crosspoints, heavy arbiter |
Hierarchical (four 4x4) | About 8 hops | 4 links | Bridge links bottleneck without locality |
Lesson | What it covers |
|---|---|
Mesh, torus, ring, crossbar and hierarchical fabrics with diameter and bisection numbers. | |
Zero-load latency in four terms, bisection caps, and Little's-law buffer sizing. | |
Dimension-order routing, the turn model, and routing versus protocol deadlock. | |
Wormhole forwarding, credit-depth sizing, and head-of-line blocking. | |
Priority, round robin and weighted shares, starvation bounds, shaping, and watchdogs. | |
A repeatable bring-up method: triggers, fabric-versus-endpoint split, one fix, recheck. |
Bisection per direction decides, because it bounds cross-partition traffic. Closing the mesh into a torus doubles it from 8 to 16 links at the price of long wrap wires, far cheaper than a crossbar.