DenseChip

Computer Architecture · All levels

Accelerator Architectures

Senior-level architecture guidance for selecting accelerator patterns, dataflows, memory strategies, and integration contracts in production SoCs.

Section goal

Choose and integrate accelerator architectures that deliver KPI gains with predictable system-level behavior.

Mechanism to narrate

  • Architecture choices must be justified by workload structure, not trend-driven templates.

  • Dataflow and memory placement determine efficiency more than isolated compute peak.

  • Integration contracts with fabric, software, and verification decide schedule risk.

Senior course bar for this section

  • Every topic should end with an architecture decision, not only concept recall.

  • Every fix should state expected metric movement and likely regression surface.

  • Every open assumption should have an owner, tag, and review date.

  • Every recurring issue should become a methodology guardrail or checklist item.

  1. accelerator-patterns/ — Accelerator Design Patterns

  2. dataflow-architectures/ — Dataflow Architecture Choices

  3. memory-locality/ — Memory Locality and Hierarchy Co-Design

  4. accelerator-integration/ — Accelerator Integration into SoC

Related topics

Key takeaways

  • Senior accelerator ownership means balancing throughput, programmability, area, and lifecycle maintainability.

Section deep dive

Accelerators win on locality and bandwidth contracts, not peak OPS alone.

Concept diagram

diagram
ACCELERATOR DATAFLOW

Host CPU ── commands ──► Queue / scheduler
   ▲                         │
   │ completion              ▼
Coherent memory ◄── DMA ── Local SRAM ──► Compute array
                         ▲       │
                         └ tiles ┘

Peak TOPS matters only when data reaches the array at the needed rate.

Metric graph

diagram
UTILIZATION BREAKDOWN

compute active   ██████████████████  58%
DMA wait         ██████████          31%
host sync        █████               15%
cache/coherency  ████                12%
idle bubbles     ███████             22%

Low utilization is usually a system integration problem.

Metrics and artifacts

  • accelerator utilization

  • DMA bandwidth

  • kernel launch overhead

  • coherency invalidation rate

Mini case study

NPU met TOPs target but end-to-end inference slow — DMA and weight fetch dominated. Architecture added on-chip SRAM tile and double-buffering.

Debug branches

  • If util low, check launch overhead and host sync first.

  • If BW high, examine weight layout and sparsity support.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

  • Connect every architecture claim to a workload and measurable metric.

  • State verification and PPA impact before proposing design changes.

Common pitfalls

  • Feature-driven design without MPKI/IPC/bandwidth evidence.

  • Ignoring coherency and NoC traffic in cache and accelerator sizing.

Practice this lesson