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Course contents

  • Architecture Metrics Reference
  • Workload Taxonomy for Architects
  • Architecture Glossary
  • Computer Architecture Cheatsheet
  • Pipeline Fundamentals14
  • Memory Hierarchy15
  • NoC and Interconnect Architecture6
  • Coherency and Memory Ordering9
  • Performance Analysis9
  • Accelerator Architectures6
    • Accelerators for the Architect
      • When an Accelerator Pays Off
      • Dataflow Patterns as Reuse Contracts
      • Systolic Execution and Utilization Cliffs
      • Locality, Scratchpads and Tile Sizing
      • DMA and Double Buffering
      • Integration, Launch Cost and Signoff
  • SoC Architecture Tradeoffs9
  • Architecture Interview Prep14
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‹Accelerator Architectures
  1. Topics
  2. Computer Architecture
  3. Accelerator Architectures
  4. Accelerators for the Architect

Computer Architecture · All levels

Accelerators for the Architect

When an accelerator pays off, how dataflow and locality set efficiency, and what integration must guarantee.

  • 6topics
  • 6lessons

An accelerator wins when the workload has steady parallel work, the dataflow keeps operands local, and the platform cost of launching and feeding it stays below the saved compute.

Pattern

Assumes

Breaks when

Systolic / MAC array

Dense regular math with reuse

Shapes mismatch the array, sparsity grows

SIMD / vector

Wide regular loops

Lanes diverge, masks go sparse

Reduction tree

Many-to-few combines

Reduction depth exceeds accumulator residency

Streaming pipeline

Producer-consumer flow

FIFOs underrun, backpressure stalls

Launch, movement, compute and drain path.
Work flows from launch to movement to resident compute to drain; each stage can cap the whole.

Lesson

What it covers

When an accelerator pays off

Amdahl bounds plus launch and transfer costs, with kill criteria.

Dataflow patterns as reuse contracts

Weight, output and input stationary styles, with traffic counted by hand.

Systolic execution and utilization cliffs

Fill, drain and padding losses, proved by a runnable MAC pipeline.

Locality, scratchpads and tile sizing

Bytes per operation, scratchpads and tile fit against SRAM capacity.

DMA and double buffering

Overlapping transfers with compute, proved by a runnable overlap model.

Integration, launch cost and signoff

Coherency choice, launch budgets, tail latency and release gates.

Check yourself Peak array throughput doubles but end-to-end time barely moves. Name two non-compute suspects.

Transfer time and launch overhead. If tiles arrive late or each launch pays a fixed cost, the array waits and the gain stays unrealized.

Interview

State the chain in one breath: Amdahl bounds the win, reuse sets traffic, residency sets stalls, and launch plus QoS decide what ships. Every follow-up in this topic hangs off that sentence.

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