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Computer Architecture · All levels

Computer Architecture Cheatsheet

Dense reference for pipelines, caches, NoC, coherency, accelerators, and performance debug.

Architecture debug order

diagram
METRIC → MECHANISM → EXPERIMENT → CHANGE → VALIDATION

Pipeline:  IPC/CPI → stall breakdown → frontend vs backend → width/depth/OOO
Cache:     MPKI → miss penalty → capacity/conflict/compulsory → size/policy/prefetch
NoC:       latency/BW → topology/VC/QoS → routing deadlock → credits/arbitration
Coherency: traffic → false sharing → MESI/MOESI transitions → layout + line size
Accel:     util% → DMA BW → kernel launch → memory locality + coherency

Quick formulas

  • CPI = 1/IPC

  • AMAT = hit_time + miss_rate × miss_penalty

  • Bandwidth needed ≈ demand rate capped by link and DRAM capacity

  • Roofline: perf ≤ min(peak compute, memory BW × arithmetic intensity)

  • Speedup ≤ 1 / ((1-P) + P/S) — Amdahl reminder for core/accelerator debates

Pipeline cheat lines

  • Frontend bound: I-cache miss, branch mispredict, fetch width

  • Backend bound: execution ports, scheduler, long-latency ops

  • Memory bound: LSU queue, cache miss, MSHR limits

  • Deeper pipe helps only if branch + cache assumptions hold

Cache cheat lines

  • Capacity miss: working set > cache size

  • Conflict miss: too many lines compete for sets

  • Compulsory miss: first touch; prefetch may help

  • False sharing: coherence traffic without logical sharing

NoC cheat lines

  • Check VC count, credits, routing restrictions, QoS

  • Average latency hides starvation

  • Deadlock needs cycle proof, not intuition

  • Coherent writebacks can dominate 'memory' traffic

Coherency cheat lines

  • MESI: Invalid, Shared, Exclusive, Modified

  • MOESI adds Owned to reduce off-chip write traffic

  • Memory ordering ≠ cache coherence

  • Litmus tests before microarch changes on ordering bugs

PMU / top-down cheat lines

  1. Is frontend delivering uops?

  2. Is backend retiring uops?

  3. Is bad speculation wasting work?

  4. Is memory the limiter?

  5. Is the kernel compute or memory bound on roofline?

Interview one-liners

diagram
Strong: "On workload X, MPKI rose from 8 to 14, mostly L2 conflict misses after layout change."
Weak:   "The cache is slow."

Strong: "p99 latency spikes when DMA and coherent reads share a VC."
Weak:   "The NoC is congested."

Strong: "Roofline shows kernel B is memory-bound; wider SIMD is not the first fix."
Weak:   "We need more cores."

Related topics

Architecture deep dive

Computer architecture decisions must be tied to workload metrics and silicon constraints.

Concept diagram

diagram
ARCHITECTURE DECISION LOOP

workload → metric → bottleneck mechanism → experiment → design option → validation

Metric graph

diagram
METRIC TREND

bad run  ██████████
base     ██████████████
target   ████████████████████

Metrics and artifacts

  • IPC/CPI

  • latency

  • bandwidth

  • power

  • area

  • verification risk

Mini case study

A senior architecture review converts a vague performance issue into a metric, a mechanism, an experiment, and a bounded design choice.

Debug branches

  • If the metric is not workload-specific, do not accept the conclusion.

  • If the fix has no PPA and verification statement, the review is incomplete.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Practice this lesson