One page for debug order, bounds, and formulas. Every formula matches the metrics reference.
Frontend bound: I-cache miss, branch mispredict, or fetch width starves decode. Backend bound: execution ports, scheduler depth, or long-latency ops stall retire. Memory bound: LSU queue depth, cache miss, or MSHR limits cap MLP.
Virtual channels isolate traffic classes; VC-partitioned routing with an acyclic channel dependency graph breaks routing deadlock. Protocol-level deadlock still needs separate request and response classes.
CPI equals 1 over IPC. AMAT equals hit time plus miss rate times miss penalty. Delivered bandwidth is demand rate capped by link and DRAM realities. Roofline says performance stays under the lower of peak compute and bandwidth times intensity. Amdahl caps speedup by the unimproved fraction.
Strong: on workload X, MPKI rose from 8 to 14, mostly L2 conflict misses after the layout change. Weak: the cache is slow.
Strong: p99 latency spikes when DMA and coherent reads share a virtual channel. Weak: the NoC is congested.
Strong: the roofline shows kernel B is memory bound, so wider SIMD is not the first fix. Weak: we need more cores.