Computer Architecture · All levels

Architecture Interview Prep

Whiteboard framework, timed scenarios, and cross-topic senior Q&A for architecture roles.

How to use this section

Run scenarios with a timer. Narrate metric → mechanism → experiment → change → validation.

Mechanism to narrate

  • Open with the failing or target metric

  • Draw the minimal block diagram

  • List 2–3 hypotheses ordered by likelihood

  • Propose one experiment per hypothesis

  • Close with tradeoffs and validation plan

  1. arch-whiteboard-framework — delivery structure

  2. scenario-cache-storm — 45 min cache/MPKI crisis

  3. scenario-noc-deadlock — 45 min NoC debug

  4. architecture-interview-qa-bank — 25 cross-topic questions

Section deep dive

Interview performance is structured metric-first reasoning under time pressure.

Concept diagram

diagram
WHITEBOARD ANSWER SHAPE

1. Workload and metric
2. Block diagram
3. Bottleneck hypothesis tree
4. Experiment plan
5. Design options and tradeoffs
6. Validation / regression

If you skip step 1, the rest sounds generic.

Metric graph

diagram
ANSWER QUALITY LADDER

5/5  metric + mechanism + experiment + tradeoff + validation
4/5  correct mechanism, weak validation
3/5  concept knowledge, no workload
2/5  feature list
1/5  buzzwords

Metrics and artifacts

  • one-slide metric summary

  • block diagram

  • hypothesis list

  • validation workloads

Mini case study

Strong candidates name the workload and baseline IPC before drawing any pipeline stage.

Debug branches

  • If stuck, restate metric and ask for constraints.

  • If pressured, present options with tradeoffs not single answer.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

  • Connect every architecture claim to a workload and measurable metric.

  • State verification and PPA impact before proposing design changes.

Common pitfalls

  • Feature-driven design without MPKI/IPC/bandwidth evidence.

  • Ignoring coherency and NoC traffic in cache and accelerator sizing.