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Course contents

  • Architecture Metrics Reference
  • Workload Taxonomy for Architects
  • Architecture Glossary
  • Computer Architecture Cheatsheet
  • Pipeline Fundamentals14
  • Memory Hierarchy15
  • NoC and Interconnect Architecture6
  • Coherency and Memory Ordering9
  • Performance Analysis9
  • Accelerator Architectures6
  • SoC Architecture Tradeoffs9
    • PPA at System Level
    • Power and Energy for the Architect
      • Dynamic Switching Power
      • Static and Leakage Power
      • DVFS and the Energy-Delay Tradeoff
      • Energy per Operation and the Memory Gap
  • Architecture Interview Prep14
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‹Power and Energy for the Architect
  1. Topics
  2. Computer Architecture
  3. SoC Architecture Tradeoffs
  4. Power and Energy for the Architect
  5. Energy per Operation and the Memory Gap

Computer Architecture · All levels

Energy per Operation and the Memory Gap

Energy per op, the memory energy gap and a clock-gating toy model.

On this page

    From power to energy per operation

    Power divided by throughput is energy per operation. It is the efficiency number architects compare across designs.

    Assume the lesson-1 block: 0.288 W at 3 GHz and one instruction per cycle. Each instruction costs 96 pJ.

    Diagram
    E_per_op = P / (f x IPC)
      = 0.288 W / (3e9 Hz x 1)
      = 9.6e-11 J = 96 pJ

    The compute-memory energy gap

    Moving data costs far more than computing on it. Textbooks commonly place an off-chip access roughly two orders of magnitude above a simple on-chip ALU operation.

    The ratios below are illustrative orders of magnitude of that textbook class, not vendor measurements. Keep data local and reuse it.

    Operation

    Illustrative relative energy

    Integer ALU op

    1x

    Register file access

    A few x

    On-chip SRAM access

    Tens of x

    Off-chip DRAM access

    About 100x

    Assume one memory-heavy kernel with this illustrative split. The shares sum to 100 percent up to rounding.

    Sink

    Share of task energy

    Off-chip DRAM movement

    45 percent

    On-chip SRAM and registers

    25 percent

    Datapath arithmetic

    15 percent

    Clock and interconnect

    15 percent

    Toy model: clock gating

    The model below counts toggles over a fixed 16-cycle pattern with activity on every third cycle. It is a runnable toy of activity-based energy accounting.

    design.sv
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    module tb_clock_gate_activity;
      localparam int N = 16;
      localparam int CLK_COST = 1;
      localparam int DATA_COST = 1;
      localparam int STATIC_COST = 1;
      int errors = 0;
      int ungated_clk = 0;
      int gated_clk = 0;
      int data_toggles = 0;
      int e_ungated = 0;
      int e_gated = 0;
    
      initial begin
        for (int i = 0; i < N; i++) begin
          ungated_clk = ungated_clk + CLK_COST;
          e_ungated = e_ungated + STATIC_COST;
          e_gated = e_gated + STATIC_COST;
          if ((i % 3) == 0) begin
            gated_clk = gated_clk + CLK_COST;
            data_toggles = data_toggles + DATA_COST;
          end
        end
        e_ungated = e_ungated + ungated_clk + data_toggles;
        e_gated = e_gated + gated_clk + data_toggles;
        if (ungated_clk != 16) errors++;
        if (gated_clk != 6) errors++;
        if (data_toggles != 6) errors++;
        if (e_ungated != 38) errors++;
        if (e_gated != 28) errors++;
        if ((e_ungated - e_gated) != 10) errors++;
        if (errors == 0) $display("PASS: gating trims modeled energy from 38 to 28 units on the 16-cycle pattern");
        else $display("FAIL: %0d count checks differ", errors);
        $finish;
      end
    endmodule

    Gating saves 10 of 38 units, about 26 percent. The static share accrues every cycle, so it caps the saving.

    Common mistakes

    Common pitfall

    Quoting energy per ALU operation as the cost of a workload ignores movement. In memory-heavy kernels the DRAM and interconnect shares above dominate the ALU share.

    Interview

    Likely probe: where to add one SRAM near the datapath. Answer: it converts repeated DRAM trips into SRAM hits, attacking the largest share in the table above.

    Check yourself Throughput doubles at fixed power. What happens to energy per operation?

    It halves. The same power spread over twice the operations costs half per operation.

    Check yourself The toy pattern runs 16 cycles with activity on every third cycle starting at cycle 0. How many active cycles is that?

    Six: cycles 0, 3, 6, 9, 12 and 15.

    Related topics

    • Dynamic Switching Power

    • DVFS and the Energy-Delay Tradeoff

    • Memory bandwidth and latency

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    See also

    • Dynamic Switching Power
    • Static and Leakage Power