Power and Energy for the Architect · arch

Computer Architecture · All levels

Every performance gain has a power cost. This topic turns that cost into numbers the architect can budget.

Component	Scales with	Architectural lever
Switching power	C, V squared, frequency, activity	Clock gating, DVFS, simpler datapaths
Short-circuit and glitch power	Transition time, logic depth	Cell choice, glitch-aware logic
Static leakage power	Voltage, temperature, transistor count	Power gating, multi-Vt, retention

Total power split into switching and static parts, both feeding energy.

Switching and static power add to total power; energy is total power times delay.

Lesson	What it covers
Dynamic Switching Power	The C V squared f alpha formula with worked numbers.
Static and Leakage Power	Leakage sources, power gating and retention with worked numbers.
DVFS and the Energy-Delay Tradeoff	Voltage-frequency scaling, energy-delay product and race-to-halt.
Energy per Operation and the Memory Gap	Energy per op, the compute-memory gap and a gating toy model.

Check yourself A block halves its activity factor at fixed C, V and f. What happens to switching power, and what happens to leakage?

Switching power halves with activity. Leakage is unchanged, because it does not depend on switching.