DenseChip

Computer Architecture · All levels

Coherency and Memory Ordering

Build coherent multiprocessor systems that preserve correctness across private caches, interconnect protocols, and weak/strong memory ordering contracts.

Section goal

Translate abstract memory-consistency rules into protocol, microarchitecture, and debug mechanisms that hold under stress.

Mechanism to narrate

  • Coherency and ordering are related but distinct contracts and must be validated separately.

  • Protocol elegance is irrelevant if forward progress or observability is weak in real workloads.

  • Debug hooks for ownership transitions and ordering fences are mandatory for post-silicon triage.

Senior course bar for this section

  • Every topic should end with an architecture decision, not only concept recall.

  • Every fix should state expected metric movement and likely regression surface.

  • Every open assumption should have an owner, tag, and review date.

  • Every recurring issue should become a methodology guardrail or checklist item.

  1. mesi-overview/ — MESI Fundamentals and Variants

  2. ace-chi-introduction/ — ACE and CHI Protocol Introduction

  3. memory-ordering-models/ — Memory Ordering Models in Practice

  4. coherency-debug/ — Coherency and Ordering Debug Playbook

Related topics

Key takeaways

  • A robust coherent system is proven by edge-case behavior, not by normal-case throughput.

Section deep dive

Coherency protocols trade traffic, latency, and verification complexity.

Concept diagram

diagram
MESI STATE SKETCH

        read miss          write
 Invalid ─────────► Shared ───────► Modified
    ▲                 │  ▲             │
    │ invalidate      │  │ downgrade   │ writeback
    └─────────────────┘  └─────────────┘

The interview bar is not naming states; it is explaining traffic and ordering.

Metric graph

diagram
COHERENCY TRAFFIC STACK

read shared      █████████████  42%
read exclusive   ███████        21%
invalidates      ██████████     31%
writebacks       █████          14%
snoop retries    ███            8%

False sharing often appears as invalidation spikes.

Metrics and artifacts

  • coherency transaction rate

  • snoop/filter efficiency

  • ordering violation tests

  • false sharing counters

Mini case study

Performance regression traced to false sharing on a counter array — coherency traffic exploded. Architecture fix: per-core counters + periodic merge, not faster NoC alone.

Debug branches

  • If rare SW bug, run litmus and ordering tests before microarch changes.

  • If traffic high, profile sharing patterns at cache-line granularity.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

  • Connect every architecture claim to a workload and measurable metric.

  • State verification and PPA impact before proposing design changes.

Common pitfalls

  • Feature-driven design without MPKI/IPC/bandwidth evidence.

  • Ignoring coherency and NoC traffic in cache and accelerator sizing.

Practice this lesson